Qualcomm Incorporated

Nagarjuna Duvvuru

Tao Wang

Jian Liang

Chunlin Wang

Gur Prasad Srivastava

Vinay Reddy Venumuddala

A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.

Zero pixel culling for graphics processing

A voltage and frequency scaling system for a processor is provided that may be implemented in dedicated logic or in software. The various voltage and frequency settings for the processor comprise a set of performance settings. The system includes a profiler module that maps each performance setting to a workload range for the processor. The profiler module also maps each workload range to a profiled throughput for the processor. Using a predicated average throughput from the mapping, the voltage and frequency scaling system advantageously selects from the performance settings and commands the processor to operate according to the selected performance setting.

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Bengaluru, India

Nagarjuna Duvvuru