Avago Technologies International Sales Pte. Limited

Samsung Electronics Co., Ltd.

Avago Technologies General IP (singapore) Pte. Ltd.

Plx Technology, Inc.

Avago Technologies General IP Pte, Ltd.

Nagarajan Subramaniyan

Shreyas Shah

Jack Regula

Jeffrey Michael Dodson

Jeffrey S Earl

George Apostol, Jr

Ramdas P Kachare

Fred Worley

Wentao Wu

Harry Rogers

Rajendran Vishwanathan

Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC and extensible via cxloverethernet (COE) protocols

Heterogeneous architecture, delivered by cxl based cached switch SOC and extensible via cxloverethernet (COE) protocols

Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC

Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC

A system is disclosed. An upstream interface enables communication with a processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for data, and a storage device acceleration module to assist the acceleration module in executing the acceleration instruction.

SSD architecture for FPGA based acceleration

A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a physical function (PF) to expose the storage device, a second function to expose the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. A downstream filter associated with the downstream port may intercept an acceleration instruction associated with a downstream Filter Address Range (FAR) received from the storage device and deliver the acceleration instruction to the APM-F, the acceleration instruction being. An upstream filter associated with the upstream port may intercept an acceleration instruction received from the processor and deliver the second acceleration instruction to the APM-F. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a Peripheral Component Interconnect Express (PCIe) link, and a processor. The memory stores Expansion Read-Only Memory (Expansion ROM) boot instructions for a host. The processor identifies devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link. The processor also generates a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, and provides responses describing the synthetic PCIe hierarchy to a host. Furthermore, the processor acquires PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and provides boot instructions to the host from the memory based on the PCIe read requests.

Virtual expansion ROM in a PCIe environment

A method of sharing of a function of a device with a plurality of hosts through a PCIe switch is provided. A function on a device is presented to a first host and a second host through the switch. Read and write on the function's register set within the first host and within the second host are captured, thereby enabling a management system of the switch to create a shadow copy of the first host register sets and second host register sets. The creation of sets of shadow queues on the management system is enabled. The first set of shadow queues of the first set of registers is used to direct read and write operations from the first host to the function. The second set of shadow queues of the second set of registers is used to direct read and write operations from the second host to the function.

Switch with synthetic device capability

A PCIe switch implements a logical device for use by connected host systems. The logical device is created by logical device enabling software running on a host management system. The logical device is able to consolidate one or more physical devices or may be entirely software-based. Commands from the connected host are processed in the command and response queues in the host and are also reflected in shadow queues stored in the management system. A DMA engine associated with the connected host is set up to automatically trigger on queues in the connected (local) host. Commands are sent to the physical devices to complete the work and a completion signal is sent to the management software and a response to the work is sent directly to the connected host, which is not aware that the logical device is non-existent and is implemented by software in the management system.

PCI express switch with logical device capability

A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.

Method and apparatus for securing and segregating host to host messaging on PCIe fabric

A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.

Growing community of inventors

San Jose, CA, United States of America

Nagarajan Subramaniyan