University of South Florida

Nagarajan Ranganathan

Santosh K Aditham

Koustav Bhattacharya

Raghu Sastry

Jarred Adam Ligatti

Narender Hanchate

Mario Kovac

Matthew Morrison

Himanshu Thapliyal

A runtime attack can be detected on a big data system while processes are executed on various nodes. A behavior profile can be maintained for tasks or processes running on different nodes. The existence of a call variance in one of the traces for one of the behavior profiles can be determined. A memory variance can also be detected in one of the behavior profiles. A runtime attack has occurred when both the memory variance and the call variance are determined to exist.

Detecting threats in big data platforms based on call trace and memory access patterns

Various examples of methods and systems are provided for an attack detection system that can detect attacks in big data systems. The attack detection system can include security modules coupled to data nodes of the big data system. The attack detection system can identify a process executing on the respective data node. A process signature can be generated for the process executing on the data node. A determination of whether a big data system is being attacked can be based at least in part on a comparison of the process signature with at least one other process signature for the same process executing on another security module. The other process signatures are received via secure communication from the other security module.

Systems and methods for detecting attacks in big data systems

A runtime attack can be detected on a big data system while processes are executed on various computing devices. A behavior profile can be maintained for tasks or processes running on different computing devices. The existence of a call variance in one of the traces for one of the behavior profiles can be determined. A memory variance can also be detected in one of the behavior profiles. A runtime attack has occurred when both the memory variance and the call variance are determined to exist.

An adiabatic dynamic differential logic circuit is provided for mitigating a differential power analysis (DPA) attack on a secure integrated chip including a plurality of transistors configured to perform each of a plurality of two-input logical output calculations, wherein each of the two-input logical output calculations results in a minimal differential power of the logic circuit. In one embodiment, a high-performance adiabatic dynamic differential logic circuit is provided which is optimized for very high operating frequencies. In another embodiment, a body-biased adiabatic dynamic differential logic circuit is provided which utilizes transistor body biasing to improve the switching time and differential power of the design.

Adiabatic dynamic differential logic for differential power analysis resistant secure integrated circuits

The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.

Methodology and apparatus for reduction of soft errors in logic circuits

A novel conservative gate especially suiting a Quantum Dot Cellular Automata (QCA) majority voter-based design. The input-to-output mapping of the novel conservative QCA (CQCA) gate is: P=A; Q=AB+BC+AC [MV(A,B,C)]; R=A'B+A&#x2032;C+BC [MV(A&#x2032;,B,C)], where A, B, C are inputs and P, Q, R are outputs, respectively. A method of transferring information in a quantum-dot cellular automata device is also provided.

Conservative logic gate for design of quantum dot cellular automata circuits

An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.

Method and apparatus for reducing leakage in integrated circuits

A fully pipelined VLSI circuit structure for implementing the JPEG baseline image compression standard. The circuit structure exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The entire is designed to be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024.times.1024 color images.

VLSI circuit structure for implementing JPEG image compression standard

The edit distance between two strings a.sub.1, . . . , a.sub.m and b.sub.1, . . . , b.sub.n is the minimum cost s of a sequence of editing operations (insertions, deletions and substitutions) that convert one string into the other. This invention provides VLSI circuit structure for computing the edit distance between two strings over a given alphabet. The circuit structure can perform approximate string matching for variable edit costs. More importantly, the circuit structure does not place any constraint on the lengths of the strings that can be compared. It makes use of simple basic cells and requires regular nearest-neighbor communication, which makes it suitable for VLSI implementation.

VLSI circuit structure for determining the edit distance between strings

A VLSI structure and method for polygon recognition that identifies an unknown two dimensional contour as corresponding to one or more of a plurality of known two dimensional contours. The VLSI architecture comprises a systolic processing system comprising a plurality of matrix element processing elements (MEPEs), and an array of feasible match processing elements (FMPEs) interconnected with selected MEPEs and with each other in a predetermined configuration. The plurality of MEPEs receive inputs comprising pairs of edge length ratios and corresponding threshold values for consecutive edges of the unknown contour and for each of the known polygon contours. Each MEPE (i) receives edge length ratios and threshold values for a pair of edges of the unknown contour and a known polygon contour, (ii) determines a dissimilarity value for the pair of edges, and (iii) directs this value to a selected FMPE of the array. The dissimilarity value is determined using the absolute differences between respective edge length ratios and threshold values for the pair of edges. The array of FMPEs determines feasible matches between pairs of consecutive edges of the unknown contour and the known polygon contours and delivers outputs related thereto, and a comparator device compares such outputs and delivers a final output which is indicative of the longest number of consecutive edges, above a predetermined minimum, for which feasible matches have occurred between the unknown contour and a known polygon contour.

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Tampa, FL, United States of America

Nagarajan Ranganathan