Infineon Technologies Ag

Infineon Technologies North America Corp.

Nagaraj V Dixit

Prasanth Perugupalli

Larry C Leighton

Thomas W Moller

Cynthia Blair

Gordon Ma

Robert Bartola

Tom Moller

Cindy Blair

Tan Pham

Stan Lopuch

A semiconductor power device comprises a flange, a die having a gate, a source, and a drain. The source is electrically coupled to the flange. A drain matching circuit is located on the flange having an input, an output and a bias input, the input being coupled with the drain. The drain matching circuit comprises an inductor coupled in series with a first capacitor between the drain and flange and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and in parallel with the first capacitor through a second inductor. An input terminal is mechanically coupled to the flange and electrically coupled with the gate, an output terminal is mechanically coupled to the flange and electrically coupled with the output of the drain matching circuit, and an input bias terminal is mechanically coupled to the flange and electrically coupled with the drain through the bias input.

Semiconductor power device and RF signal amplifier

A power transistor, having: a semiconductor having an electrode formed thereon, wherein the electrode comprises a plurality of interdigitated transistors each having input and output terminals; a first output blocking capacitor having a first terminal electrically coupled to the output terminals of the interdigitated transistors of the semiconductor and a second terminal electrically coupled to ground; and a second output blocking capacitor having a first terminal electrically coupled to the first terminal of the first output blocking capacitor and a second terminal electrically coupled to ground. A method for amplifying signals, the method having: forming a power transistor on a semiconductor, wherein the power transistor comprises a plurality of interdigitated transistors; shunting an output signal from the plurality of interdigitated transistors; and double-shunting an output signal from the plurality of interdigitated transistors, wherein the shunting and double-shunting generates first and second harmonic terminations at a die plane of the power transistor.

Output match transistor

A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Bond wire tuning of RF power transistors and amplifiers

Conventional broadband RF power amplifiers use a &frac14; wavelength transmission line to decouple the gate bias DC source from the gate circuitry and a second &frac14; wavelength transmission line to decouple the drain bias DC source from the drain circuitry, taking up considerable printed circuit board space. A novel broadband RF power amplifier uses a transistor with separate terminals for injection of gate bias and drain bias DC sources, eliminating the need for &frac14; wavelength transmission lines, thereby freeing up space and allowing higher density packaging. The power amplifier transistor can be implemented with a single die circuit or multiple die circuits operating in parallel.

RF power transistor with internal bias feed

Disclosed are systems and methods for automatic biasing of LDMOS devices at turn-on. The invention provides bias point setting with compensation for hot carrier effects each time the LDMOS device is turned on and also provides temperature compensation during operation of the device. The systems and methods of the invention are scalable such that a plurality of LDMOS devices may simultaneously have their bias points set, and temperature compensation provided.

Growing community of inventors

Gilbert, AZ, United States of America

Nagaraj V Dixit