Intel Corporation

Altera Corporation

Intel Corproation

Nagabhushan Chitlur

Linda J Rankin

Pratik M Marolia

Utkarsh Y Kakaiya

Michael C Adler

Sundar Nadathur

Eliezer Weissmann

Ravishankar Iyer

Andrew J Herdrich

Alon Naveh

Dheeraj R Subbareddy

Inder M Sodhi

Eugene Gorbatov

Russell Jerome Fenger

David A Koufaty

Ganapati Srinivasa

Joshua David Fender

Dennis Ryan Bradford

Stephen S Chang

Henry M Mitchel

Scott D Hahn

Paolo L Narvaez

Gaurav Khanna

Joseph J Grecco

Mishali Naik

Paul Brett

Abirami Prabhakaran

Paul M Stillwell, Jr

Aaron J Grier

Francesc Guim Bernat

Rajesh M Sankaran

David Stewart Dunning

Susanne M Balle

Maruti Gupta

Alexander Bachmutsky

Mohan Nair

Ling Liu

Gene F Young

Kevin W Bross

Josh Triplett

Dave Dunning

Sharath Raghava

Harsha Gupta

Shunyu Zhu

Dirk Blevins

Andrzej Kuriata

Kalyan Kondapally

Todd Langley

Michael T Werstlein

Jonathan Lo

Zhihong Yu

Steven Zhang

Rohan Menezes

Mariano Aguirre

Sudeep Puligundla

Hongbin (Michael) Liao

Chuanhua Song

Peter Yiannacouras

Radhakrishna Sripada

Michael Werstlein

Methods, apparatus, and software for remote storage of hardware microservices hosted on other processing units (XPUs) and SOC-XPU Platforms. The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). Software, via execution on the SOC, enables the platform to pre-provision storage space on a remote storage node and assign the storage space to the platform, wherein the pre-provisioned storage space includes one or more container images to be implemented as one or more hardware (HW) microservice front-ends. The XPU/FPGA is configured to implement one or more accelerator functions used to accelerate HW microservice backend operations that are offloaded from the one or more HW microservice front-ends. The platform is also configured to pre-provision a remote storage volume containing worker node components and access and persistently store worker node components.

Remote storage for hardware microservices hosted on XPUs and SOC-XPU platforms

A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.

Flushing cache lines involving persistent memory

A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

Modular accelerator function unit (AFU) design, discovery, and reuse

A server having a host processor coupled to a programmable coprocessor is provided. One or more virtual machines may run on the host processor. The coprocessor may be coupled to an auxiliary memory that stores virtual machine (VM) states. During live migration, the coprocessor may determine when to move the VM states from the auxiliary memory to a remote server node. The coprocessor may include a coherent protocol home agent and state tracking circuitry configured to track data modification at a cache line granularity. Whenever a particular cache line has been modified, only the data associated with that cache line will be moved to the remote server without having to copy over the entire page, thereby substantially reducing the amount of data that needs to be transferred during migration events.

Methods and apparatus for accelerating virtual machine migration

There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.

Unified address space for multiple links

Apparatuses and systems associated with expansion card design with a coherent connector to provide for coherent communication are disclosed herein. In embodiments, a circuit card may comprise an integrated circuit (IC), a first connector to couple the IC to a processor of a computer device, the first connector to provide for non-coherent communication between the IC and the processor, and a second connector to couple the IC to the processor, the second connector to provide for coherent communication between the IC and the processor. Other embodiments may be described and/or claimed.

Circuit card with coherent interconnect

There is disclosed in one example an accelerator apparatus, including: a programmable region capable of being programmed to provide an accelerator function unit (AFU); and a platform interface layer (PIL) to communicatively couple to the AFU via an intra-accelerator protocol, and to provide multiplexed communication with a processor via a plurality of platform interconnect interfaces, wherein the PIL is to provide abstracted communication services for the AFU to communicate with the processor.

Platform interface layer and protocol for accelerators

A processor to facilitate acceleration of instruction execution is disclosed. The processor includes a plurality of execution units (EUs), each including an instruction decode unit to decode an instruction into one or more operands and opcode defining an operation to be performed at an accelerator, a register file having a plurality of registers to store the one or more operands and an accelerator having programmable hardware to retrieve the one or more operands from the register file and perform the operation on the one or more operands.

Execution unit accelerator

A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a register that is mapped to the logic block for storing interrupt status information of the logic block.

Using memory cache for a race free interrupt scheme without the use of 'read clear' registers

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Apparatus and method for heterogeneous processors mapping to virtual cores

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

Hetergeneous processor apparatus and method

A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.

Dynamic accelerator reconfiguration via compiler-inserted initialization message and configuration address and size information

Method and apparatus for coherent device initialization and access

According to some embodiments, data to be exchanged via a system input output interface may be determined at a processor. It may then be arranged to exchange the data via a coherent input output device coupled to a coherent system interconnect. Other embodiments are described.

Coherent input output device

Growing community of inventors

Portland, OR, United States of America

Nagabhushan Chitlur