Apple Inc.

Texas Instruments Corporation

Anobit Technologies Ltd.

Intel Corporation

Naftali Sommer

Ofir Shalvi

Uri Perlmutter

Micha Anholt

Dotan Sokolov

Eyal Gurgi

Yoav Kasorla

Avraham Poza Meir

Oren Golov

Itay Lusky

Shai Winter

Moshe Neerman

Daniel Wajcer

Tal Inbar

Yigal Bitran

Ariel Yagil

Julian Vlaiko

Zvi Reznic

Ariel Maislos

Gil Semo

Yosef Bendel

Eli Haim

Ronen Dar

Or Ordentlich

Barak Rotbard

Yael Shur

Barak Baum

Srinath Hosur

Anuj Batra

Deric Wayne Waters

Yonathan Tate

Liran Brecher

Moti Teitel

Etai Zaltsman

Lior Ophir

Mordechai Segal

Mor Miller

Nohik Semel

Meir Dalal

Ran Senderovitz

Amir Peleg

Sriram Hariharan

Alon Paycher

Axel Dominique Berny

Shai Ojalvo

Sreeraman Anantharaman

Naor Goldman

Stas Mouler

Nir Sasson

Eli Yazovitsky

Rafi Dalla Torre

Yair Schwartz

Michael Tsohar

Alon Elhanati

Roi Faust

Uri Garbi

Asaf Landau

Oren Peles

Doron Burshtein

Liran Erez

Alex Radinski

Yoav Kasoria

Maya Barkon

Tsafrir Kamelo

Raanan Yechezkel

Eli Ochayon

Melamed Oded

Armand Chocron

A sink device is configured to establish a Bluetooth connection with a source device. The sink device receives a transmission from the source device that includes a plurality of data blocks, an item of check information, and a plurality of parity blocks during a transmission time duration. The sink device determines, prior to receiving an entirety of the transmission, whether at least one of received data blocks includes an error based on at least the item of check information and, when the at least one of the received data blocks includes the error and prior to receiving all of the plurality of parity blocks, the sink device performs an error correction operation on a first one of the received data blocks based on a first one of the parity blocks.

Bluetooth transmission using low density parity check

A storage device includes circuitry and memory cells that store data in Np programming levels of threshold voltage values. The circuitry defines NRv threshold-sets, each includes Ns read thresholds that define Ns+1 zones, produces Ns readouts by reading, from a target WL, using the NS read thresholds, a target page that was stored encoded using an Error Correction Code (ECC), and produces a reference readout by reading the target page using optimal read thresholds. The circuitry identifies Np programming levels of memory cells in a neighbor WL for classifying target cells in the target WL into Np&#xb7;NRv cell-groups. The circuitry calculates, per zone, Np LLR values, for the respective Np programming levels, based on the reference readout, the Ns readouts and the classification, assigns the LLR values to the target cells, and recovers the target page by applying to the assigned LLR values soft decoding for decoding the ECC.

Performance in reading memory cells affected by neighboring memory cells

An apparatus includes an interface and a decoder. The interface is configured to receive a code word, produced in accordance with an Error Correction Code (ECC) represented by a set of parity check equations. The code word includes a data part and a redundancy part, and contains one or more errors. The decoder is configured to hold a definition of a partial subgroup of the parity check equations that, when satisfied, indicate that the data part is error-free with a likelihood of at least a predefined threshold, to decode the code word by performing an iterative decoding process on the parity check equations, so as to correct the errors, and during the iterative decoding process, to estimate whether the data part is error-free based only on the partial subgroup of the parity check equations, and if the data part is estimated to be error-free, terminate the iterative decoding process.

Iterative decoding with early termination criterion that permits errors in redundancy part

A decoder includes circuitry and a soft decoder. The circuitry is configured to receive channel hard decisions for respective bits of a Generalized Low-Density Parity Check (GLDPC) code word that includes multiple component code words, including first and second component code words having one or more shared bits, to schedule decoding of the GLDPC code word, and following the decoding, to output the decoded GLDPC code word. The soft decoder is configured to receive the channel hard decisions corresponding to the first component code word, to further receive soft reliability measures that were assigned to the shared bits in decoding the second component code word, and to decode the first component code word based on the channel hard decisions and the soft reliability measures.

GLDPC soft decoding with hard decision inputs

A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

Programming schemes for multi-level analog memory cells

A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

Redundant data storage schemes for multi-die memory systems

A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.

Management of data storage in memory cells using a non-integer number of bits per cell

A method includes storing data in memory cells by programming the memory cells with respective values. The memory cells are read in multiple readout operations that each compares the programmed values to at least first and second read thresholds, while keeping the first read threshold fixed throughout the readout operations and perturbing only the second read threshold between the readout operations. A preferred value for the second read threshold is estimated based on the multiple readout operations.

Adaptation of high-order read thresholds

A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

Memory device with internal signal processing unit

Techniques and systems for position determination using narrowband signals are disclosed. A disclosed technique includes receiving, at a wireless device, signals that are transmitted at different times, each of the signals having a different carrier frequency and representing a different subchannel of a wireless channel; determining estimated magnitudes of the subchannels based respectively on the signals; determining estimated group delays of the subchannels based respectively on the signals; determining an estimated channel frequency response of the wireless channel based on the estimated magnitudes and the estimated group delays; determining a propagation delay of the signals based on the estimated channel frequency response; and generating position information based on the propagation delay.

Positioning techniques for narrowband wireless signals under dense multipath conditions

A method for operating a memory () includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells () of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.

Reading memory cells using multiple thresholds

A method for data storage includes reading from a memory device data that is stored in a group of memory cells as respective analog values, and classifying readout errors in the read data into at least first and second different types, depending on zones in which the analog values fall. A memory quality that emphasizes the readout errors of the second type is assigned to the group of the memory cells, based on evaluated numbers of the readout errors of the first and second types.

Estimating flash quality using selective error emphasis

A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

Mitigation of data retention drift by programming neighboring memory cells

Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

High-performance ECC decoder

Growing community of inventors

Rishon Le-Zion, Israel

Naftali Sommer