International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Infineon Technologies Ag

Naftali Eliahu Lustig

Ronald G Filippi

Andrew Herbert Simon

Samuel S Choi

Kaushik Chanda

Stephan Grunow

Ping-Chuan Wang

Daniel C Edelstein

Sampath Purushothaman

Baozhen Li

Fuad Elias Doany

Kangguo Cheng

Chih-Chao Yang

Anthony K Stamper

Theodorus E Standaert

Yun Yu Wang

Griselda Bonilla

Junjing Bao

Elbert Emin Huang

Stephen Edward Greco

Thomas W Dyer

James A Culp

Wai-Kin Li

Rasit Onur Topaloglu

Jane M Shaw

Erdem Kaltalioglu

Harold John Hovel

Alessandro Cesare Callegari

William J Cote

Chao-Kun Hu

Dan Moy

Tien-Jen Cheng

Soon-Cheon Seo

Timothy Joseph Dalton

Katherine Lynn Saenger

Kenneth Parker Rodbell

John Anthony Fitzsimmons

Tze-Chiang Chen

Xiao Hu Liu

Stephen Ellinwood Luce

Carlos Juan Sambucetti

Ning Lu

Ho-Ming Tong

Terence Lawrence Kane

Matthew S Angyal

William L Guthrie

Lijuan Zhang

David Earle Seeger

Douglas Andrew Buchanan

Jim Shih-Chun Liang

Andrew T Pomerene

Donis G Flagello

Robert G Schad

Samuel S S Choi

Peter D Roper

Douglas C Latulipe, Jr

Aaron J Fleischman

Howard M Clearfield

Fredric D Bailey

Christopher M Scherpereel

Keith Randal Pope

Vlasta A Brusic

Andrew Tae Kim

Lee Matthew Nicholson

Mark A Jaso

Atsushi Ogino

Tuhin Sinha

Daewon Yang

Xiaomeng Chen

Wilma Jean Horkans

Paul M Feeney

Frank Benjamin Kaufman

Sujatha Sankaran

Glenn A Biery

Tze-man Ko

Samuel Sung Shik Choi

Thomas Edwin Sandwick

Nan Jing

Zheng G Chen

Randall M Feenstra

Pegeen M Davis

David B Thompson

Birenda Nath Agarwala

Vincent Mcgahay

Brett H c/o Ibm United Kingdom Ltd Ip Engel

Ann c/o Ibm United Kingdom Ltd Ip Law Mcdonald

A metal insulator metal capacitor and method for fabricating a metal insulator metal capacitor (MIMcap) are disclosed. A first level metal pattern is embedded in a first dielectric layer over a substrate. The first level metal pattern has a top surface co-planar with a top surface of the first dielectric layer. In a selected etch step, either one of the first metal pattern or the first dielectric is etched to form a stepped top surface. A conformal insulating layer on the stepped top surface. The MIMcap is formed on the conformal insulating layer in a conformal manner.

High performance metal insulator metal capacitor

Interconnect structures having enhanced reliability is provided in which an electrically conductive structure having a line portion and a via portion is formed utilizing a subtractive process. In some embodiments, a non-conductive barrier liner is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls and a topmost surface of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure. In other embodiments, a conductive barrier spacer is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure.

Interconnect architecture with enhanced reliability

Embodiments of the present invention are directed to a new crack stop system and a method for providing an interlayer dielectric (ILD) crack bifurcation in semiconductor back-end-of-line (BEOL). In a non-limiting embodiment of the invention, a crack stop is formed over a substrate. The crack stop can span one or more dielectric layers. A topologically interlocking composite structure is formed adjacent to the crack stop and over the substrate. The topologically interlocking composite structure spans the one or more dielectric layers. A capping film is formed over the topologically interlocking composite structure and one or more metal interconnect layers are formed over the capping film. The composite structure includes a bulk matrix material and embedded inclusions. To promote crack bifurcation, materials of the inclusions and bulk matrix material are selected to ensure that the Young's modulus of the inclusions is greater than the Young's modulus of the bulk matrix material.

Crack bifurcation in back-end-of-line

Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.

Airgap vias in electrical interconnects

An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.

Back end of line (BEOL) time dependent dielectric breakdown (TDDB) mitigation within a vertical interconnect access (VIA) level of an integrated circuit (IC) device

Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.

Interconnect structure having subtractive etch feature and damascene feature

A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Stacked via structure for metal fuse applications

A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

Forming air gap

A method of forming an integrated metal line and interconnect. The method may include forming a first trench in a first ILD exposing a lower metal line, the first ILD is above a substrate, and the lower metal line is in the substrate; forming a first barrier layer in the first trench; forming an integrated metal layer (including a first metal line and a first via) on the first barrier layer; forming a first hardmask on the integrated metal layer; forming an isolation trench in the first hardmask and in the first metal line; forming a second barrier layer in the isolation trench; removing a portion of the second barrier layer from a bottom of the isolation trench exposing the first ILD; and forming a second ILD on the second barrier and in the isolation trench, where a bottom of the second ILD is in the first ILD.

Subtractive etch interconnects

A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

Detecting a void between a via and a wiring line

A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Back-end electrically programmable fuse

A method for an interconnect structure including: forming a hard mask layer on a semiconductor substrate having a wiring line; patterning the hard mask layer to form a patterned hard mask layer having a hard mask layer opening; depositing a dielectric stack on the patterned hard mask layer and in the hard mask layer opening; patterning the dielectric stack to form a via opening aligned with the hard mask layer opening and to expose the wiring line through the via opening and the hard mask layer opening, a bottom of the via opening defined by the hard mask layer having the hard mask layer opening; and filling the via opening and the hard mask layer opening with a metal to form a via in contact with the wiring line.

Bottom self-aligned via

Interconnect structure having substractive etch feature and damascene feature

Growing community of inventors

Croton on Hudson, NY, United States of America

Naftali Eliahu Lustig