Intel Corporation

Nafees Kabir

Manish Chandhok

Kevin Lai Lin

Elijah V Karpov

Hui Jae Yoo

Richard E Schenker

Miriam Ruth Reshotko

Richard F Vreeland

Michael Christenson

Noriyuki Sato

Eungnak Han

Ramanan Chebiam

Tristan A Tronic

Jeffery D Bielefeld

Gurpreet Singh

Matthew V Metz

Christopher J Jezewski

Florian Gstrein

Rami Hourani

Colin T Carver

William Brezinski

James M Blackwell

Carl H Naylor

Jiun-Ruey Chen

Gilbert W Dewey

Willy Rachmady

Patrick R Morrow

Aaron D Lilak

Charles Henry Wallace

Kevin O'Brien

Paul Anton Nyhus

Ehren Mannebach

Anh Phan

Brennen Karl Mueller

Nityan Labros Nair

Brandon Jay Holybee

Xuanxuan Chen

Giselle Elbaz

Sasikanth Manipatruni

Ian A Young

Abhishek A Sharma

Tanay Gosavi

Seung Hoon Sung

Uygar E Avci

Kaan Oguz

Mauro J Kobrinsky

Leonard P Guler

Christopher J Wiegand

Shriram Shivaraman

David N Shykind

Stephanie A Bojarski

Angeline Smith

Tofizur Rahman

Benjamin Buford

Tayseer Mahdi

Makram Abd El Qader

Joseph D'silva

James Munro Blackwell

Gauri Nabar

Thomas Christopher Hoff

Shaun Mills

Rohan Patil

Gate-all-around integrated circuit structures having backside contact with enhanced area relative to an epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures. The conductive structure is along an entirety of a bottom of the one of the first epitaxial source or drain structures, and the conductive structure can also be along a portion of sides of one of the first epitaxial source or drain structures.

Gate-all-around integrated circuit structures having backside contact with enhanced area relative to epitaxial source

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Subtractively patterned interconnect structures for integrated circuits

Disclosed herein are IC structures, packages, and devices that include recesses processed via selective growth. An example integrated circuit (IC) structure, includes a first dielectric material, a second dielectric material on the first dielectric material, and a recess in the second dielectric material, wherein the recess includes a bottom, a top, and sidewalls. The IC further includes a first material within the recess and at a bottom of the recess, wherein the first material includes a metal and oxygen, a self-assembled monolayer (SAM) material, or an organic material, and a second material within the recess and between the first material and the top of the recess, wherein the second material is in contact with the sidewalls of the recess.

Integrated circuit structure with filled recesses

Integrated circuitry comprising devices electrically coupled through a plurality of interconnect levels in which lines of a first and second interconnect level are coupled through a planar slab via. An interconnect line may include a horizontal line segment within one of the first or second interconnect levels, and the slab via may be a vertical line segment between the first and second interconnect levels. A planar slab via may comprise one or more layers of conductive material, which have been deposited upon a planarized substrate material that lacks any features that the conductive material must fill. A planar slab via may be subtractively defined concurrently with a horizontal line of one or both of the first or second interconnect levels.

Planar slab vias for integrated circuit interconnects

Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.

Directed self-assembly enabled subtractive metal patterning

A method of fabricating an integrated circuit structure comprises depositing an oxide insulator layer over a substrate having fins. A gate trench is formed within the oxide insulator layer with the fins extending above a surface of the oxide insulator layer within the gate trench. A semiconducting oxide material is deposited to conformally cover the oxide insulator layer, including on top surfaces and sidewalls of both the gate trench and the fins. A gate material is deposited to conformally cover the semiconducting oxide material, including on top surfaces and sidewalls of both the gate trench and the fins. An angled etch is performed to remove the gate material selective to the semiconducting oxide material from sidewalls of the gate trench, but not from sidewalls of the fins.

Angled etch to enable tin removal from selected sidewalls

Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.

Directed self-assembly enabled patterning over metal layers using assisting features

Methods for fabricating metallization stacks with one or more self-aligned staggered metal lines, and related semiconductor devices, are disclosed. Methods and devices are based on providing a spacer material conformal to bottom metal lines of a first layer of a metallization stack. By carefully designing parameters of the deposition process, the spacer material may be deposited in such a manner that, for each pair of adjacent bottom metal lines of the first layer, an opening in the spacer material is formed in a layer above the bottom metal lines (i.e., in the second layer of the metallization stack), the opening being substantially equidistant to the adjacent bottom metal lines of the first layer. Top metal lines are formed by filling the openings with an electrically conductive material, resulting in the top metal lines being self-aligned and staggered with respect to the bottom metal lines.

Metallization stacks with self-aligned staggered metal lines

Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

Contact over active gate structures with metal oxide-caped contacts to inhibit shorting

An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

Interconnect structures and methods of fabrication

Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

Methods and structures for improved electrical contact between bonded integrated circuit interfaces

Interconnect structures are disclosed. An example includes conductive traces over a first dielectric layer, dielectric helmet structures over top surfaces of the conductive traces, and a second dielectric layer over the helmet structures. Spaces between adjacent ones of conductive traces are devoid of material. A bottom surface of the second dielectric layer is between top surfaces of the dielectric structures and bottom surfaces of the helmet structures, or co-planar with the top surface of the helmet structures, but the airgap extends above tops of the conductive traces. Another example includes a dielectric adjacent to upper sections but not lower sections of conductive traces, so as to provide airgaps between adjacent lower sections. Alternatively, a first dielectric material is adjacent the upper sections and a second compositionally different dielectric material is adjacent the lower sections. In either case, the sidewalls of the upper sections of the interconnect features may include scalloping.

Helmet structures for semiconductor interconnects

A method for fabricating an integrated circuit comprises forming one or more conductive features supported by pillars of a first insulating layer in a first metal layer. One or more vias are formed in a via layer, the one or more vias over and on the first metal layer and in electrical connection with ones of the one or more conductive features. Subsequent to via formation, air gaps are between adjacent ones of the one or more conductive features in the first metal layer to separate the one or more conductive features. A second insulating layer is formed over the one or more conductive features and over the one or more vias, such that the second insulating layer covers the first metal layer and the via layer while bridging over the air gaps, wherein tops the air gaps are substantially coplanar with tops of the one or more conductive features.

Maskless air gap enabled by a single damascene process

Growing community of inventors

Portland, OR, United States of America

Nafees Kabir