Dongbu Electronics, Co. Ltd.

Dongbu Anam Semiconductor, Inc.

Naewon Lee

In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding. A potting solution is coated on the substrate and the second chip and installed thereon a heat spreader and then cured. An encapsulation resin is coated on a bottom surface of the substrate and electrically interconnected a third chip to the bottom surface of the substrate through a bump and an inner lead bump.

Multi-stack chip size packaging method

In a double side stack packaging a plurality of chips, a hole is formed in a substrate. A first chip is attached to a bottom surface of the substrate by using a thermo compression and is electrically interconnected to terminals formed at sidewall of the hole using a wire bonding. Next, an epoxy is coated on the substrate and the first chip and a first heat spreader is installed thereon and then the epoxy is cured. Thereafter, a second chip is attached to a top surface of the substrate by using the epoxy and is electrically interconnected to terminals formed on the substrate using the wire bonding. And then, an encapsulation resin is coated on the substrate and the first chip and a second heat spreader is installed thereon and then the epoxy is cured.

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Seoul, South Korea

Naewon Lee