Samsung Electronics Co., Ltd.

Seoul National University

Nae-in Lee

Geum-Jong Bae

Hwa-sung Rhee

Dong-Suk Shin

Hoi-Sung Chung

Sang-Su Kim

Tae-hee Choe

Sang-Hoon Ahn

Jong-Min Baek

Young-Tak Kim

Chul-Woong Lee

Byung-Hee Kim

Jongmin Baek

Wookyung You

Sangho Rha

Pan-Kwi Park

Jong-Ho Lee

Sanghoon Ahn

Geum-jong Bae

Ki-chul Kim

Hong-Jae Shin

Jin-Nam Kim

Rak-Hwan Kim

Sang-su Kim

Ho-jin Lee

Eun-Ji Jung

Jong-Jin Lee

Sung-Ho Kim

Jin-Hee Kim

Myung-Sun Kim

Dong-Hyun Roh

In-Wook Cho

Geo-Myung Shin

Woo-Kyung You

Kyung-wook Lee

Hyun-Chul Kang

Jae-ouk Choo

Seong-Jin Nam

Hwa-Sung Rhee

Hyung-suk Jung

Chang-Wook Moon

Jin-ho Chun

Seong-min Son

Joong S Jeon

Kwang-Wook Koh

Yun-Seok Kim

Sang Su Kim

Jeong-gi Jin

Young-joon Moon

Jum-yong Park

Seo-woo Nam

Ki Chul Kim

Ho-Yun Jeon

Dae-Hong Ko

Jongho Lee

Young-wook Park

Kwang-Jin Moon

Ha-Jin Lim

Jung-il Lee

Young-Gun Ko

Jong-ho Lee

Thomas Oszinda

Tsukasa Matsuda

Yi-Koan Hong

Bong-young Yoo

Sang-Ho Rha

Hyeong-Joon Kim

Hyun-deok Yang

Seok-Joo Doh

Ho Young Lee

Young-sun Kim

Jung-hyun Lee

Suk-Pil Kim

Dongsuk Shin

Woo-Jin Lee

Pankwi Park

Jae-Won Chang

Hee-Sung Kang

Moon-han Park

Donghyun Roh

Woo-Sik Kim

Yun-Hee Lee

Young-wug Kim

Jae-Yoon Yoo

Byung Hee Kim

Sang Hoon Ahn

Ja-Eung Koo

Jeon-Il Lee

Chong-Kwang Chang

Ki-Chul Kim

Byung-Iyul Park

Se-Young Cho

Hwa Sung Rhee

Kyung-Min Chung

Kee-Young Jun

Seo-Woo Nam

Kwan-young Oh

Hyung-Jun Jeon

Young-ju Park

Chulwoong Lee

A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

Semiconductor chip

A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

Semiconductor devices

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

Semiconductor device having a trench with a convexed shaped metal wire formed therein

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Semiconductor devices including a capping layer

Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

Semiconductor device and method of fabricating the same

According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Semiconductor devices and methods of forming the same

A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.

Fan out wafer level package type semiconductor package and package on package type semiconductor package including the same

A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

Methods of manufacturing semiconductor devices including conductive structures

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.

Growing community of inventors

Seoul, South Korea

Nae-in Lee