Lg Semicon Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Nae-Hak Park

Chang-Jae Lee

Young-Jin Song

Yun-Hee Kim

Young Kwon Jun

Yong Kwon Kim

Jin-Won Park

Dae-Won Suh

A method for reducing surface defects of a semiconductor substrate comprising selectively etching an insulation film formed on a semiconductor substrate and forming a contact hole, forming a conductive layer in a contact hole and on the upper surface of the insulation film, performing a Chemical Mechanical Polishing process on the conductive layer to expose the upper surface of the insulation film and forming a conductive layer plug in the contact hole, forming an oxide film on the upper surface of the conductive plug, and washing the conductive layer plug and the surface of the insulation film. In order to reduce surface defects of a semiconductor substrate, an oxide film is formed on the surface of the semiconductor substrate during the Chemical Mechanical Polishing process or after the Chemical Mechanical Polishing process, so that the efficiency of the post-washing process is heightened and the surface defects of the substrate is reduced.

Method for reducing surface defects of semiconductor substrates

A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Fabrication method of semiconductor device with diagonal capacitor bit line

Semiconductor device with diagonal capacitor bit line and fabrication

A method and apparatus for controlling the amount of ozone concentration in the layers of a film depositing system and the multi-layered structure produced thereby, whereby the concentration of ozone in each layer gradually changes from a low ozone concentration in the first deposited layer to a high ozone concentration in the last deposited layer.

TEOS-O.sub.3 oxidizing film depositing system and process for supplying

Process for supplying ozone (O.sub.3) to TEOS-O.sub.3 oxidizing film

A method for fabricating wiring in a semiconductor device in which a conductor line and a contact hole are formed by self-alignment, includes the steps of: forming an insulating layer on a substrate; forming an etch-step layer on the insulating layer; etching the etch-stop layer of a wiring region connected to a window and the insulating layer to a predetermined thickness; forming a mask layer on the etch-stop layer and the insulating layer; etching the mask layer to remove the mask layer at the central part of the window; and etching the insulating layer of the central part of the window so as to form a contact hole. By applying such a method, a highly improved reliability can be obtained, and a process thereof is simplified by a single photolithography. Also, the contact hole is formed by self-alignment in the lengthwise direction and in the vertical direction of the conductor line.

Method for fabricating wiring in semiconductor device

Growing community of inventors

Seoul, South Korea

Nae-Hak Park