Lsi Logic Corporation

Nadya Strelkova

Stanislav V Aleshin

Ranko L Scepanovic

Kunal N Taravade

Neal Patrick Callan

John V Jensen

Ebo H Croffie

Sergei Rodin

Marina Igorevna Medvedeva

Marina M Medvedeva

Santosh S Menon

Evgueny E Egorov

Sergey V Uzhakov

Jaroslav V Kalinin

Ilya Golubtsov

A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selected minimum distance from a polygon edge opposite the critical edge, constructing a critical region bounded by the critical edge and the polygon edge opposite the critical edge, comparing the critical region to a potential defect criterion, and generating as output a location of the critical region when the critical region satisfies the potential defect criterion.

Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction

The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the OPC mask. The method also includes classifying each cell of at least one of the target layer and the OPC mask layer as either repeating or non-repeating, and for each repeating cell, recognizing geometric points in the target layer to determine quality measuring groups. The method also includes simulating the OPC mask layer based on the quality measuring groups, measuring edge placement errors (EPEs) based on at least one of the geometric points, and providing an EPE layer representing EPEs greater than an EPE threshold.

Method and system for analyzing the quality of an OPC mask

A method for verifying reticle enhancement technique latent image sensitivity to mask manufacturing errors. The method includes the steps of revising a polygon based on mask CD distributions to provide a virtual mask, imaging the virtual mask to obtain response function statistical parameters, and comparing the statistical parameters to process tolerance requirements. Preferably, the method includes the steps of simulating an aerial and/or latent image of the virtual mask, calculating response functions based on the mask image simulation, collecting measurements and calculating statistical parameters based on the response functions, and comparing the statistical parameters with design rule requirements (i.e., for DI yield percentage for required mask manufacturing specification). The virtual mask is obtained by using mask CD distribution to induce statistical variations to layouts which have passed through the conventional OPC procedure.

Method and apparatus for verifying the post-optical proximity corrected mask wafer image sensitivity to reticle manufacturing errors

A method of measuring the quality of a simulated aerial image includes receiving as input a mask pattern for a chip design, simulating an aerial image of the mask pattern, calculating an error area representative of a deviation between an ideal boundary of the chip design and a boundary of the simulated aerial image, calculating maximum and average end-of-line deviations between the ideal boundary of the chip design and the boundary of the simulated aerial image, and displaying a worst quality area in the simulated aerial image as a function of the error area and the maximum and average end-of-line deviations for visual inspection.

Quality measurement of an aerial image

A circuit, gate, or device parameter simulation includes data on the initial conditions of manufacture, including illumination conditions on a stepper, material parameters for processing conditions, and chip layout. Optical effects and processing tolerances may be accounted for in the simulation of the final device performance characteristics. The circuit, gate, or device parameter simulation may incorporate optical proximity code software. Simulated active and passive components are generated by the circuit, gate, or device parameter simulation from the simulated patterned layers on the substrate. Feedback may be provided to the circuit, gate, or device parameter simulation to optimize performance.

Device parameter and gate performance simulation based on wafer image prediction

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Portland, OR, United States of America

Nadya Strelkova