Xilinx, Inc.

Agere Systems Inc.

Nader Sharifi

Sagheer Ahmad

Ahmad R Ansari

Brian C Gaide

James F Anderson

Hiep The Pham

James D Wesselkamper

Aman Gupta

Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

System and method for secure deconstruction sensor in a heterogeneous integration circuitry

Various embodiments of a hybrid class AB super follower circuit are provided. One embodiment is a follower circuit comprising: an input node for receiving an input voltage signal; an output node for driving a capacitive load based on the input voltage signal; a transistor Mhaving a gate terminal connected to the input node for receiving the input voltage signal, a source terminal connected to the output node, and a drain terminal; a feedback loop comprising a second transistor M, a third transistor Mand a fourth transistor M, wherein: the gate and source terminals of the second transistor Mare connected to a current source I, and the drain terminal of the second transistor Mis connected to the output node; the source terminal of the third transistor Mis connected to the current source Iand the drain terminal of the third transistor Mis connected to a current source I; the gate terminal of the fourth transistor Mis connected to the drain terminal of the third transistor M, the drain terminal of the fourth transistor Mis connected to the output node, and the source terminal of the fourth transistor Mis connected to a ground; and a replica bias circuit for providing a voltage bias signal to the gate terminal of the third transistor.

Hybrid class AB super follower

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San Jose, CA, United States of America

Nader Sharifi