Lsi Logic Corporation

Nader Fakhry

Viswanathan Lakshmanan

Jayendra P Gagvani

A method of debugging an IKOS model. The method includes mapping information contained in either a .pin or .lde file or both into corresponding files which are more user-friendly, readable and editable. Preferably, a .v file which is readable to create a schematic view of the cell is also created and the schematic view can be viewed and analyzed. Then, the one or more user-friendly files which have been created can be read and edited, and the .pin and/or the .lde file is re-created. Then, a tool is used to analyze the .pin and .lde files again and determine whether there is a functional or timing failure.

Method to debug IKOS method

A method of translating a register transfer level code model includes receiving as inputs a user defined primitives map file, a truth table map file, a gate primitives map file, a register transfer level description file of a library cell, a standard delay format file, and a pin order information file for the register transfer level code model; creating data structures for a VITAL model; parsing at least one of the user defined primitives map file, the truth table map file, the gate primitives map file, the register transfer level description file, and the standard delay format file to generate an equivalent VITAL model in the data structures created for the VITAL model wherein the VITAL model is functionally equivalent to the register transfer level code model; and generating as output a VITAL model file from the data structures created for the VITAL model.

Verilog to vital translator

A program translates an EDIF netlist that defines a circuit into a data file containing a predetermined subset of the circuit-defining data. The program operates on netlists that define designs and library cells. The data file is useful to describe the circuit, or a portion of the circuit, in a simpler and more intuitive format, so that users unfamiliar with the circuit or with EDIF format can quickly understand the circuit components and connectivity. The subset of circuit data is parsed out of the EDIF netlist and stored in the data file. The data file is useful for extracting and clearly describing the instances connected to a specified signal. The data file is also useful for generating a graphical or textual display of the circuit. A user may specify primary ports, signals, global ports, and cell instances to focus the subset of circuit data on the portion of the circuit of interest. Signals may be traced on a graphical display. Another program can create an EDIF netlist from the data file. Methods for extracting and formatting this data receive command line or interactive input from a user.

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Portland, OR, United States of America

Nader Fakhry