Intel Corporation

Daedalus Prime LLC

Daedauls Prime LLC

Nadav Shulman

Efraim Rotem

Doron Rajwan

Eliezer Weissmann

Alon Naveh

Avinash N Ananthakrishnan

Nir Rosenzweig

Itai Feit

Ryan Donovan Wells

Esfir Natanzon

Tomer Ziv

Inder M Sodhi

Zeev Offen

Tal Kuzi

Dorit Shapira

Daniel Yellin

Yona Perets

Hisham Abu Salah

Hisham Abu-Salah

Guy Wolf

Alexander Gendler

Ilan Sutskover

Yoni Aizik

Arik Gihon

Paul S Diefenbaugh

Michael Mishaeli

Jeffrey A Carlson

Ofer J Nathan

Guy M Therien

Gal Leibovich

Ido Melamed

Krishnakanth Venkata Sistla

Barnes Cooper

Ronny Ronen

Ohad Falik

Ankush Varma

Boris Ginzburg

Jorge Pedro Rodriguez

Daniel J Ragland

Israel Diamand

Asaf Rubinstein

Philip R Lehwalder

Jawad Haj-Yihia

Itay Franko

Yevgeni Sabin

Elkana Korem

Amit Gur

Niv Tokman

Vijay S R Degalahal

Maxim Levit

Bart Plackle

Amit Gabai

Tsung-Yuan Charles Tai

Ren Wang

Christian Maciocco

Ittai Anati

Robert E Gough

Vivek Garg

Dan Baum

Lily Pao Looi

Michael Zelikson

Douglas Raymond Moran

Hisham Shafi

Sharon Levy

Kosta Luria

Ariel Berkovits

Ariel Szapiro

Adwait Purandare

Nimrod Angel

Ariel Gur

Arye Albahari

Eric Dehaemer

Allen W Chu

Shmuel Zobel

Nir Misgav

David Pawlowski

Hanan Shomroni

Shani Rehana

Peter A Dice

Michael Bitan

Erik C Bjorge

Eliezer Wiessman

Sameer Desai

Yakir Ovadia

Assaf Ganor

Andrey Gabdulin

Ori Levy

Louis Draghi

Oren Zonensain

Roman Rechter

Almog Reshef

Eli Efron

David Ben Shimon

Nir Levitin

Shmulik Zobel

Dorit Shpira

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Controlling operating voltage of a processor

Methods, apparatus, and articles of manufacture to dynamically configure overclocking frequency have been disclosed. An example apparatus include a clock rate adjuster to cause a processor core to operate at a first overclocked clock rate; a comparator to compare a sensed temperature corresponding to the processor core to a threshold; and the clock rate adjuster to, when the sensed temperature satisfies the threshold, decrease a clock rate of the processor core from the first overclocked clock rate by a user-defined amount, the decreased clock rate being above a normal operating clock rate of the processor core.

Methods and apparatus to dynamically configure overclocking frequency

Controlling operating frequency of a processor

Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

Application priority based power management for a computer device

A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

Leakage degradation control and measurement

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

Mechanism for saving and retrieving micro-architecture context

In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.

Hardware unit for controlling operating frequency in a processor

In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

System, apparatus and method for controlling a processor based on effective stress information

In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.

Performing soft throttling and hard throttling in a processor

Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency

In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

Programmable power management agent

In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Dynamically controlling cache size to maximize energy efficiency

Growing community of inventors

Tel Mond, Israel

Nadav Shulman