Marvellworld Trade Ltd.

Habana Labs Ltd.

Nadav Klein

Shlomo Raikin

Ron Shalev

Michael Weiner

Sergei Gofman

Ran Halutz

Hunglin Hsu

Chia-Hung Chien

Junhua Xu

A computational apparatus includes a memory unit and Read-Modify-Write (RMW) logic. The memory unit is configured to hold a data value. The RMW logic, which is coupled to the memory unit, is configured to perform an atomic RMW operation on the data value stored in the memory unit.

Processing-memory architectures performing atomic read-modify-write operations in deep learning systems

A Dynamic Random Access Memory (DRAM) controller includes a memory interface and a processor. The memory interface is configured to communicate with a DRAM including one or more memory banks. The processor is configured to receive Input/Output (I/O) commands, each I/O command addressing a respective memory bank and a respective row within the memory bank to be accessed in the DRAM, to further receive one or more indications, indicative of likelihoods that a subsequent I/O command will address a same row in a same memory bank as a previous I/O command, to adaptively set, based on the indications, a policy of deactivating rows of the DRAM, and to execute the I/O commands in the DRAM in accordance with the policy.

DRAM controller with adaptive precharge policy

Growing community of inventors

Tel Aviv, Israel

Nadav Klein