Tamba Networks, Inc.

Other

Nad Karim

Soren Pedersen

Rony Kurniawan

Elton J Cairns

Paul H Vroomen

An apparatus, method and system are disclosed, relating to a dual-chemistry battery subsystem having different battery chemistries and performance properties, and relating to an algorithm of charging and discharging the battery subsystem. For an EV application, the battery subsystem is a tailored solution that combines two different battery configurations, a first battery configuration and a second battery configuration, to satisfy the unique needs of different driving modes and performance profiles of an EV, such as a typical workday commute versus an occasional extended range trip on the weekend. The present disclosure provides intelligent control and heuristics to maximize useful energy on a wide variety of battery applications.

Electrically rechargeable, dual chemistry, battery system for use in plug-in or hybrid electric vehicles

Disclosed are a method, non-transitory medium, and system of a tunable design of an Interlaken region of an integrated circuit (IC). In one embodiment, a method comprises modeling a design abstraction of an Interlaken sub-circuit of an integrated circuit as a register transfer level (RTL) code within a data processing device, wherein a first stage of sequential logic in the RTL code is associated with a first stage of combinational logic in the RTL code. The method further comprises implementing, through a processor and based on a timing parameter input into a synthesis tool associated with the RTL code, a selective bypass or a selective enablement of the first stage of sequential logic. Still further, the method comprises synthesizing, through the processor, a netlist from the RTL code, wherein the first stage of sequential logic is sequentially bypassed or sequentially enabled.

Tunable design of an interlaken region of an integrated circuit

Disclosed are a method, non-transitory medium, and system of a tunable design of an Ethernet region of an integrated circuit (IC). In one embodiment, a method comprises modeling a design abstraction of an Ethernet sub-circuit of an integrated circuit as a register transfer level (RTL) code within a data processing device, wherein a first stage of sequential logic in the RTL code is associated with a first stage of combinational logic in the RTL code. The method further comprises implementing, through a processor and based on a timing parameter input into a synthesis tool associated with the RTL code, a selective bypass or a selective enablement of the first stage of sequential logic. Still further, the method comprises synthesizing, through the processor, a netlist from the RTL code, wherein the first stage of sequential logic is sequentially bypassed or sequentially enabled.

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Palo Alto, CA, United States of America

Nad Karim