Adesto Technologies Corporation

Other

Arizona State University

Nad Edward Gilbert

Shane Charles Hollmer

John Dinh

Derric Lewis

John Ross Jameson

Michael N Kozicki

Narbeh Derhacobian

Ishai Naveh

Daniel Wang

Juan Pablo Saenz Echeverry

Janet Wang

John Ross Jameson, Iii

Random number generator systems and method for tuning a randomness characteristic of the system are described. The random number generator system includes at least one programmable metallization cell (PMC) device and is configured to provide a random output word based on random telegraph noise caused by the at least one PMC device.

Tunable true random number generator using programmable metallization cell(s)

A memory device can include a plurality of bit lines; plurality of memory elements coupled to the bit lines, each memory element including a memory layer formed between two electrodes, the memory layer being programmable between a plurality of different resistance states by creation and removal of conductive regions therein by application of electric fields; and at least one sense amplifier (SA) configured to compare a first value, corresponding to a resistance state of a first memory element, to a second value, corresponding to a resistance state of a second memory element.

Memory devices and methods for storing single data value in multiple programmable resistance elements

A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.

Read operations and circuits for memory devices having programmable elements, including programmable resistance elements

Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells, where each of the resistive switching memory cells is configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and to be erased to a high resistance state by application of a second voltage in a reverse bias direction; and (ii) a sensing circuit coupled to at least one of the plurality of resistive memory cells, where the sensing circuit is configured to read a data state of the at least one resistive memory cell by application of a third voltage in the forward bias direction or the bias reverse direction.

Sensing data in resistive switching memory devices

Structures and operations of a resistive switching memory device are described herein. In one embodiment, a resistive switching memory device can include: a plurality of resistive memory cells, each configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and erased to a high resistance state by application of a second voltage in a reverse bias direction; a plurality of common plates, each being connected to a subset of the resistive memory cells; a command detector configured to detect a write command to be executed as a first and second write operations; and a write controller configured to perform the first write operation on each resistive memory cell in a selected subset, and to perform the second write operation on at least one of the resistive memory cells in the selected subset based on the detected write command.

Common plate switching reduction in resistive switching memory devices

A method can include determining a data value stored in a memory element of a memory cell array based on the length of time required to cause a property of the memory element to change. A memory device can include a plurality of elements programmable into at least two different states; and an electrical bias section that applies sense conditions to a selected element; and a sense section configured to distinguish between the two different states according to whether a change in property occurs in the selected element within a predetermined time under the sense conditions.

Memory devices, circuits and methods having data values based on dynamic change in material property

A method can include electrically programming memory elements between first and second states; and reading data from the memory elements by applying electrical sense conditions; wherein a memory element in the first state takes a longer time to undergo a change in property under the sense conditions than a memory element in the second state.

Memory devices and methods for read and write operation to memory elements having dynamic change in property

Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.

Programmable window of operation for CBRAM

A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element. In other embodiments, a memory device can include both standard and strong read operations, where strong read operations apply more energy to a selected memory element than a standard read operation.

A memory device can include a plurality of programmable elements; at least one sense circuit that generates sense data values from detected impedances of accessed programmable elements; and at least one data store circuit that stores initial data values from the at least one sense circuit, and stores output data values from the at least one sense circuit after check conditions have been applied to at least one programmable element. The check conditions can induce a change in impedance for programmable elements programmed to at least one predetermined state. Methods can include reading data from at least one memory cell of a memory device comprising a plurality of such memory cells; if the read data has a first value, providing such data as an output value; and if the read data has a second value, repeating access to the memory cell to confirm the read data value.

Read methods, circuits and systems for memory devices

An integrated circuit can include a plurality of programmable metallization cells (PMCs) in a memory array, each PMC comprising an ion conducting material, an active metal dissolvable in the ion conducting material, and two electrodes, a first electrode of at least one PMC being coupled to a program node; and a plurality of program and verify circuits, each including a current source section to enable at least one current path between the program node and a power supply node in a program and verify operation, and a verify signal generator circuit comprising at least a first comparator having a first input coupled to the program node, a second input coupled to receive a first reference voltage, and a comparator output to provide a verify signal that indicates a program operation is complete.

Methods of programming and erasing programmable metallization cells (PMCs)

An integrated circuit can include at least one programmable metallization cell (PMC) comprising an ion conducting material and a metal dissolvable in the ion conducting material, selectively connected to a shunt node; and a biasing circuit comprising a current source coupled to the shunt node configurable to provide a first current in a first type operation, and a voltage regulator coupled to the shunt node configured to regulate a potential at the shunt node; wherein in the first type operation, the voltage regulator shunts current with respect to the shunt node in a same direction as a current flow of the at least one PMC.

Variable impedance memory device biasing circuits and methods

A circuit may include an array having a number of programmable impedance elements that may be placed into at least two different impedance states in a write operation; and a write circuit that applies temperature varying write conditions to the array in a write operation.

Methods and circuits for temperature varying write operations of programmable impedance elements

A method can include programming a selected programmable metallization cell (PMC) by coupling the anodes of a group of PMCs to a first power supply voltage and connecting a cathode of one of PMCs of the group to a second power supply voltage with a select device; and erasing a selected PMC by coupling the anodes of a group of PMCs to the second power supply voltage and connecting the cathode of one of PMCs of the group to the first supply voltage with the select device.

An integrated circuit may include: access circuits that couple first electrodes of a plurality of programmable metallization cells (PMC) to access paths in parallel, each PMC comprising a solid ion conducting material formed between the first electrode and a second electrode; a plurality of write circuits, each coupled to a different access path, and each coupling the corresponding access path to a first voltage in response to input write data having a first value and to a second voltage in response to the input write data having a second value; and a node setting circuit that maintains second electrodes of the PMCs at a substantially constant third voltage while write circuits couple the access paths to the first or second voltages.

Growing community of inventors

Higley, AZ, United States of America

Nad Edward Gilbert