Hyundai Motor Company

Kia Motors Corporation

Kia Corporation

NackYong Joo

Dae Hwan Chun

Youngkyun Jung

Junghee Park

Jungyeop Hong

Jongseok Lee

Jong Seok Lee

Hyun Woo Noh

JongSeok Lee

Provided is a semiconductor device including a semiconductor substrate, a plurality of gate electrodes disposed on the upper surface portion of the semiconductor substrate and spaced apart from each other, a plurality of emitter electrodes disposed to be overlapped with each of the plurality of gate electrodes, and a collector electrode disposed on the lower surface of the semiconductor substrate.

Semiconductor device and three-phase inverter comprising the same

A semiconductor device includes an N+ type substrate, an N− type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate, a P type region disposed in the N− type layer and disposed on a side surface of the trench, a gate electrode disposed in the trench, and a source electrode and a drain electrode insulated from the gate electrode. The N− type layer includes a P type shield region covering a bottom surface and an edge of the trench.

Semiconductor device and method of manufacturing the same

A semiconductor device according to an embodiment of the present disclosure includes: a conductive region, an end region positioned at a portion where the conductive region ends, and a connection region positioned between the conductive region and the end region. The conductive region includes: an n+ type substrate; an n− type layer positioned at the first surface of the n+ type substrate; and a p type region positioned on the n− type layer, and a gate electrode that fills an inside of a trench penetrating the p type region and positioned in the n− type layer, and a side wall of the trench positioned at the portion where the conductive region ends is inclined.

Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (GaO) and the other includes silicon (Si).

Semiconductor module and method for manufacturing the same

A semiconductor device includes an n− type layer on a first surface of the substrate, a p type region on a part of the n− type layer, a gate on the n− type layer and the p type region, a first gate protection layer on the gate and a second gate protection layer on the first gate protection layer, a source on the second gate protection layer and the p type region, and a drain on the second surface of the substrate.

An embodiment semiconductor module includes a substrate, a heterogeneous thin film including a first semiconductor layer disposed on a first region of the substrate and a second semiconductor layer disposed on a second region of the substrate, a first semiconductor device disposed on the first semiconductor layer of the heterogeneous thin film, and a second semiconductor device disposed on the second semiconductor layer of the heterogeneous thin film, wherein one of the first semiconductor layer or the second semiconductor layer comprises gallium oxide (GaO) and the other includes silicon (Si).

A semiconductor device according to an exemplary embodiment of the present disclosure includes: an n&#x2212; type layer disposed in a first surface of a substrate; an n type layer disposed on the n&#x2212; type layer; a first electrode disposed on the n type layer, and a second electrode disposed in a second surface of the substrate, wherein an energy band gap of the n&#x2212; type layer is larger than an energy band gap of the n type layer.

A semiconductor device according to an exemplary embodiment of the present invention includes an n&#x2212; type epitaxial layer disposed on a first surface of a substrate; a p type region disposed on the n&#x2212; type epitaxial layer, an n+ type region disposed on the p type region, a gate disposed on the n&#x2212; type epitaxial layer, an oxidation film disposed on the gate, a source electrode disposed on the oxidation film and the n+ type region, and a drain electrode disposed on a second surface of the substrate. The gate includes a PN junction portion.

Semiconductor device and manufacturing method thereof

A semiconductor device may include: an n type of layer disposed on a first surface of a substrate; a p+ type of region disposed on the first surface of the substrate; a p&#x2212; type of region disposed at a top portion of the n type of layer; a first electrode disposed on the p+ type of region and the p&#x2212; type of region; and a second electrode disposed on a second surface of the substrate, wherein the side surface of the p+ type of region and the side surface of the n type of layer are in contact, and the thickness of the p+ type of region is the same as the thickness of the n type of layer and the thickness of the p&#x2212; type of region.

A semiconductor device includes an n+ type silicon carbide substrate, an n&#x2212; type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type.

Semiconductor device and method for manufacturing same

A manufacturing method of a semiconductor device is provided. The method includes sequentially forming an n&#x2212; type of layer, a p type of region, and an n+ type of region on a first surface of a substrate, forming a preliminary trench in the n&#x2212; type of layer by a first etching process and forming a preliminary gate insulating layer by a first thermal oxidation process. The method includes etching the lower surface of the preliminary trench and the preliminary second portion to form a trench by a second etching process and forming a gate insulating layer in the trench by a second thermal oxidation process. The gate insulating layer includes a first and second portion. The preliminary first portion is thicker than the preliminary second portion and the first portion. The first portion thickness is equal to the thickness of the second portion.

Manufacturing method of semiconductor device to uniformly form thickness of gate insulating layer

A semiconductor device may include an n&#x2212; type layer disposed at a first surface of an n+ type silicon carbide substrate; a p&#x2212; type region, a p type region, an n+ type region, and a p+ type region disposed at an upper portion in the n&#x2212; type layer; a gate electrode and a source electrode disposed on the n&#x2212; type layer and insulated from each other; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the source electrode is in contact with the p&#x2212; type region, the n+ type region, and the p+ type region, and the source electrode may include an ohmic junction region disposed at a contact portion of the source electrode and the n+ type region and the contact portion of the source region and the p+ type region and a Schottky junction region disposed at the contact portion of the source electrode and the p&#x2212; type region.

Semiconductor device and method manufacturing the same

A semiconductor device may include an n&#x2212; type layer sequentially disposed at a first surface of an n+ type silicon carbide substrate; a p type region disposed in the n&#x2212; type layer; an auxiliary n+ type region disposed on the p type region or in the p type region; an n+ type region disposed in the p type region; an auxiliary electrode disposed on the auxiliary n+ type region and the p type region; a gate electrode separated from the auxiliary electrode and disposed on the n&#x2212; type layer; a source electrode separated from the auxiliary electrode and the gate electrode; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the auxiliary n+ type region and the n+ type region are separated from each other, and the source electrode is in contact with the n+ type region.

A semiconductor device is provided. The device includes an n&#x2212; type layer with a trench disposed in a first surface of an n+ type silicon carbide substrate. An n+ type region and a first p type region are disposed at the n&#x2212; type layer and at a lateral surface of the trench. A plurality of second p type regions are disposed at the n&#x2212; type layer and spaced apart from the first p type region. A gate electrode includes a first and a plurality of second gate electrodes disposed at the trench and extending from the first gate electrode, respectively. A source electrode is disposed on and insulated from the gate electrode. A drain electrode is disposed on a second surface of the n+ type silicon carbide substrate. The source electrode contacts the plurality of second p type regions spaced apart with the n&#x2212; type layer disposed therein.

A semiconductor device includes: an n&#x2212; type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench formed in the n&#x2212; type layer and separated from each other; an n+ type region disposed between a side surface of the first trench and the side surface of the second trench and disposed on the n&#x2212; type layer; a gate insulating layer disposed inside the first trench; a source insulating layer disposed inside the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer, the n+ type region, and the source insulating layer; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate.

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Hanam-si, South Korea

NackYong Joo