Agere Systems Guardian Corp.

Agere Systems Inc.

Lucent Technologies Inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Other

Nace Layadi

Simon John Molloy

Sailesh Mansinh Merchant

Pradip Kumar Roy

Alvaro Maury

Isik C Kizilyalli

Larry Bruce Fritzinger

Reginald Conway Farrow

Jovin Lim

Masis Mkrtchyan

David M Boulin

Edward Belden Harris

Samir Chaudhry

Sundar Srinivasan Chetlur

Hem M Vaidya

Sidhartha Sen

Thomas Craig Esry

Mario V Pita

Sylvia Marci Luque

Kurt George Steiner

Arun Kumar Nanda

Brittin C Kane

John Martin McIntosh

Sylvia Thomas

Allen Yen

Steven Alan Lytle

Vivek Saxena

Scott Jessen

Mahjoub Ali Abdelgadir

James W Blatchford, Jr

Brian David Crevasse

Donald C Dennis

Sebastian Quek

Sebastian Ouek

Pei H Yih

A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.

Zone polishing using variable slurry solid content

A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Multi-layered semiconductor structure

The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.

Contact for use in an integrated circuit and a method of manufacture therefor

A new method is provided for the creation of an adhesion/barrier layer over which a tungsten interconnect is created. The invention reduces metal extrusion and effects of pin-holes by dividing the process of barrier material of TiN deposition into phases, whereby after about half the thickness of the required layer of TiN has been deposited, an intermediate and very thin layer of Ti is deposited. After the thin layer of Ti has been deposited, the deposition of the barrier layer of TiN is continued to the point where the required thickness for the layer of TiN has been reached.

IMP TiN barrier metal process

A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.

Method of dry etching a semiconductor device in the absence of a plasma

A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiO , where x is preferably less than 2.

Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics

The present invention provides a capacitor comprising a conductive plug comprising a top surface and exposed sidewalls, wherein the sidewalls comprise a layer selected from the group consisting of titanium and titanium nitride, and an electrode material layer over the conductive plug sidewalls, wherein the layer of electrode material is not titanium nor titanium nitride.

Capacitor for an integrated circuit

A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Method of forming an alignment feature in or on a multi-layered semiconductor structure

A method for fabricating an MOM capacitor ( ) includes forming a first conductive layer ( ) on an insulating support ( ), depositing a dielectric film ( ) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers ( ). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material ( ) around the capacitor feature. Sidewalls ( ), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

Method for in-situ removal of side walls in MOM capacitor formation

An unwanted tungsten film deposit on a Chemical Vapor Deposition chamber is cleaned by adding a mixture of at least two cleaning gases into the chamber at a predetermined temperature and pressure and in contact with said chamber walls for a sufficient length of time. The cleaning gases and reacted tungsten species are removed from the chamber by vacuum, and unreacted cleaning gases are removed by purging the chamber with an inert gas. At least one cleaning gas is selected from the group consisting of bromomethane, dibromomethane, bromoform and mixtures thereof. The temperature of the chamber is preferably at least about 300 degrees Celsius. The cleaning gases in the chamber are at a pressure in the range from about 100 to 200 Torr and the chamber is purged at a pressure in the range from about 200 to 500 Torr.

Method for cleaning tungsten from deposition wall chambers

Method of forming an alignment feature in or on a multilayered semiconductor structure

The present invention provides a method of manufacturing an interconnect structure. The method may include forming a nucleation layer, including a first metal, over a barrier layer and within an opening formed in a dielectric layer, forming an intermediate layer, including a second metal such as titanium nitride, over the nucleation layer and within the opening, and forming a plug portion layer, including the first metal, over the intermediate layer and within the opening. The first metal may be tungsten and the second metal may be a titanium nitride layer.

Method for reducing a metal seam in an interconnect structure and a device manufactured thereby

The present invention provides a method of manufacturing an integrated circuit having a capping layer over a thick metal feature. In one embodiment, the method comprises forming first and second oxide layers over the thick metal feature, forming a composite oxide layer including an oxide spacer by etching the first and second oxide layers, and forming a capping layer over the composite oxide layer. More specifically, forming the first oxide layer involves using a high density plasma (HDP) process, forming the second oxide layer involves using a plasma enhanced chemical vapor deposition (PECVD) process, and forming the composite oxide layer preferably involves etching with a reactive ion etch.

Methods for improved encapsulation of thick metal features in integrated circuit fabrication

Growing community of inventors

Singapore, Singapore

Nace Layadi