Sonics, Incorporated

Cypress Semiconductor Corporation

Netlogic Microsystems, Inc

Nabil Masri

Wolf-Dietrich Weber

Drew Eric Wingard

Chien-Chun Chou

Jay S Tomlinson

Thomas Wayne O'Connell

Michael Jude Meyer

Hari Om

Kamil Synek

Syed B Raza

Ajay Srikrishna

Steven R Narum

A circuit and method are provided that eliminate race conditions in data storage devices. Generally, the circuit includes: (i) an input latch to which an address signal (ADD) is applied; (ii) a multiplexer (MUX) to which the ADD is coupled from the input latch and through which an output is supplied to an output latch; (iii) an address valid signal (ADV) input coupled to the output latch and to which an ADV is applied to close the output latch supplying the output to a circuit output; and (iv) a middle latch coupled between the input latch and the MUX to hold the ADD applied to the MUX until the output latch closes, independent of a change in the ADD applied to the input latch. Preferably, the circuit includes control logic configured to close the middle latch on a rising edge of ADV and reopen it when the output latch closes.

Input latch circuit and method

Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.

Composing on-chip interconnects with configurable interfaces

Embodiments of methods and apparatuses for multicast handling in mixed core systems have been described. A method for multicast handling in mixed core systems includes configuring broadcast group registers located in targets. The method also includes receiving a request to create a broadcast group and creating the broadcast group. Finally, the method includes transmitting the broadcast group to targets with broadcast group registers that correspond to the broadcast group.

Scalable low bandwidth multicast handling in mixed core systems

A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.

On-chip inter-network performance optimization using configurable performance parameters

A communication system and method with configurable posting points have been described.

Communication system and method with configurable posting points

A content addressable memory (CAM) device () can sequentially apply command and key data to different sections (-to-). Within each section, CAM cores (-to-) can be sequentially activated. Current surges when transitioning from an idle state to an active state, or vice versa, can be significantly reduced with additional latency but no loss in throughput.

Reduced turn-on current content addressable memory (CAM) device and method

A content addressable memory (CAM) device () can receive a compare data value having a native word size. The compare data value can be split into smaller portions, with one portion can be applied to a first CAM block (-) and another being applied to a second CAM block (-) on a subsequent clock (CAMCLK) cycle. Activation of circuit elements in the second CAM block (-) can be conditioned on first match results (CMATCHAto CMATCHA) generated by first CAM block (-).

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Sunnyvale, CA, United States of America

Nabil Masri