Kepler Computing Inc.

Nabil Imam

Sasikanth Manipatruni

Amrita Mathuriya

Rajeev Kumar Dokania

Ikenna Odinaka

Rafael Rios

Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.

Asynchronous full-adder with majority or minority gates to generate carry-out true output

Asynchronous full-adder with majority or minority gates to generate carry-out false output

Asynchronous full-adder with majority or minority gates to generate sum false output

Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Asynchronous consensus circuit with stacked ferroelectric non-planar capacitors

Asynchronous consensus circuit with majority gate based on non-linear capacitors

Asynchronous consensus circuit with stacked linear or paraelectric planar capacitors

Asynchronous completion tree circuit using multi-function threshold gate with input based adaptive threshold

Asynchronous consensus circuit with stacked ferroelectric planar capacitors

Asynchronous consensus circuit using multi-function threshold gate with input based adaptive threshold

Asynchronous consensus circuit with stacked linear or paraelectric non-planar capacitors

Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1 V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3&#xd7; reduction compared to traditional asynchronous circuits) and provide higher throughput/mm(e.g., 2&#xd7; higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Asynchronous circuit with multi-input threshold gate logic and 1-input threshold gate

Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3&#xd7; reduction compared to traditional asynchronous circuits) and provide higher throughput/mm(e.g., 2&#xd7; higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Asynchronous circuit with majority gate or minority gate logic and 1-input threshold gate

Asynchronous circuit with threshold logic

Pull-up and pull-down networks controlled asynchronously by majority gate or minority gate logic

Pull-up and pull-down networks controlled asynchronously by threshold gate logic

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Nabil Imam