Cisco Technology, Inc.

Facebook, Inc.

Meta Platforms, Inc.

Naader Hasani

Mohammed Ismael Tatar

David Delano Ward

Hans-Juergen Schmidtke

David Richard Barach

Sreedhar Ravipalli

Shishir Gupta

Shahin Habibi

Arvind Srinivasan

James D Williams

John Joseph Williams, Jr

Harikrishna Madadi Reddy

Promode Nedungadi

John C Carney

Pankaj Kansal

Gilad Goldfarb

Najam Ahmad

Gregory Robbins Steinbrecher

A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit. The system also includes an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control and a retransmission data flow control.

Chip-to-chip interconnect with a layered communication architecture

The disclosed method may include (1) detecting, by a communication resource of a communication system, an event indicative of traffic congestion in the communication resource, where the communication resource services one or more traffic flows, and where at least one of the traffic flows causes the event, (2) sampling, by the communication resource, in relation to detecting the event, status data indicating a current status of the communication resource during each of a plurality of time intervals, (3) transmitting, by the communication resource, to a receiving device external to the communication resource to control the communication system, at least one of (a) at least a portion of the status data that is associated with the at least one of the traffic flows or (b) control information for the at least one of the traffic flows based on that status data. Various other methods and systems are also disclosed.

Systems and methods for communication system resource contention monitoring

The disclosed computer-implemented method may include (1) defining a topology of a data center network that defines an arrangement of a plurality of networking devices included in the data center network, (2) generating a routing policy for the data center network based on the defined topology, (3) deriving a forwarding information base (FIB) for each networking device based on the defined topology and the generated routing policy for the data center network, (4) compiling a data center traffic profile for the data center network that includes a set of data flows that include an amount of data that a source networking device begins to transfer to a destination networking device via the data center network at a predetermined time, and (5) executing a simulation of the data center network via the data center traffic profile. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for simulating data center network topologies

One embodiment performs longest prefix matching operations in one or more different manners that provides packet processing and/or memory efficiencies in the processing of packets. In one embodiment, a packet switching device determines a set of one or more mask lengths of a particular conforming entry of a multibit trie or other data structure that matches a particular address of a packet via a lookup operation in a mask length data structure. A conforming entry refers to an entry which has less than or equal to a maximum number of different prefix lengths, with this maximum number corresponding to the maximum number of prefix lengths which can be searched in parallel in the address space for a longest matching prefix by the implementing hardware. The packet switching device then performs corresponding hash table lookup operation(s) in parallel in determining an overall longest matching prefix for the particular address.

Longest prefix matching providing packet processing and/or memory efficiencies in processing of packets

In one embodiment, for each distribution period of time, each packet flow is assigned to a path through a packet switching device (e.g., switch fabric) with all packets of the packet flow being sent in order over the assigned path. For a next distribution period, different paths are assigned for these packet flows, with all packets being sent in order over the new corresponding selected path. In one embodiment, these paths are switched often enough to prevent congestion, yet infrequent enough so as to minimize resources for reordering. In one embodiment, the reordering is done at the egress and only for predefined high bandwidth flows (e.g., elephant flows). A distribution period indication is typically associated with each packet to identify its corresponding distribution period. In one embodiment, each routing and egress switching stage in a switching fabric performs reordering.

Packet switching device modifying paths of flows of packets taken within while outputting packets in received intra-flow order but not necessarily inter-flow order

The disclosure is directed to a system for hierarchically orchestrating network traffic including a network orchestration module and multiple device orchestration modules. The device orchestration module is configured to receive network traffic. The device orchestration module may transmit device data to the network orchestration module. The network orchestration module is configured to perform a network level orchestration to coordinate network traffic across multiple device orchestration modules based on the device data received by the device orchestration modules. The device orchestration module comprises a routing layer configured to forward network traffic to downstream computing devices. The device orchestration module includes a compute node configured to perform a device level orchestration of the network traffic between the routing nodes of the device orchestration module.

Hierarchical orchestration of a computer network

In one embodiment, processing is performed based on the result of a lookup operation that determines a matching hash bucket entry, with each of the entries of the hash table spanning at least two memories. A first portion of the matching hash bucket entry is retrieved from a first random access memory from a first hash bucket stored at a first location identified based on a first particular hash function applied to a hash key. First current information of the hash key is determined to match the first portion. A second portion of the matching hash bucket entry is retrieved from a second random access memory from a second hash bucket stored at a second location identified based on a second particular hash function applied to the hash key. Second current information of the hash key is determined to match the second portion.

Hash-based address matching

Data center rack systems are described. A data center rack system can include a rack having switches. A removable chassis can include an arrangement of interconnect such that a topology for a switch network can be implemented when the removable chassis is coupled with the switches.

Scalable switch

In one embodiment, multicast packets including, but not limited to, Bit Index Explicit Replication (BIER) multicast packets, are forwarded in a network. An independent lookup operation is performed on each destination node identified in the received packet to determine a nexthop to which to forward a copy of the packet. Typically, some or possibly all of these lookup operations are performed in parallel, in contrast to the sequential lookup and bit masking operations of previous BIER packet forwarding specifications and implementations. In one embodiment, the selection of a nexthop for a destination node is made from a set of two or more nexthop nodes on different Equal-Cost Multi-Paths (ECMPs). In one embodiment, compact data structures are used in determining how to forward the received multicast packet, with these compact data structures providing requisite forwarding information without allocating space to unassigned destination nodes.

Forwarding of multicast packets in a network

In one embodiment, a packet switching device comprises: a lookup chip including one or more processors and on-lookup chip memory, and off-lookup chip memory. In one embodiment, the lookup chip is configured to determine processing information for packets including performing a longest prefix match on a destination address of packets using progressive, exact matching of one or more single prefix length hash keys generated from the packets with entries in one or more hash tables until a matching hash table entry is found. The matching hash table entry is associated with particular information identifying how to process (e.g., manipulate, forward, drop) the corresponding packet. In one embodiment, entries of a hash table are distributed between said on-lookup chip memory and said off-lookup chip memory. In one embodiment, signatures of lookup keys are included in a hash table entry to quickly evaluate whether there is a match.

In one embodiment, packet memory and resource memory of a memory are independently managed, with regions of packet memory being freed of packets and temporarily made available to resource memory. In one embodiment, packet memory regions are dynamically made available to resource memory so that in-service system upgrade (ISSU) of a packet switching device can be performed without having to statically allocate (as per prior systems) twice the memory space required by resource memory during normal packet processing operations. One embodiment dynamically collects fragments of packet memory stored in packet memory to form a contiguous region of memory that can be used by resource memory in a memory system that is shared between many clients in a routing complex. One embodiment assigns a contiguous region no longer used by packet memory to resource memory, and from resource memory to packet memory, dynamically without packet loss or pause.

Dynamic temporary use of packet memory as resource memory

A system and method for pentad-based processing are disclosed for efficient processing of DS3 data by converting a DS3 frame to pentad and shuffling the overhead bit in the pentad. A framer searches for F-bits in detecting the column boundary alignment and M-bits in detecting the row boundary alignment to produce a control signal to a barrel shifter for adjusting the overhead bit position to the most significant bit position of a pentad. The F-bits and M-bits alignments require that F-bits or M-bits are detected in a predetermine number of consecutive frames. Upon proper framing, a converter converts the pentad back to a DS3 frame at the output for processing with other interfaces.

Growing community of inventors

San Jose, CA, United States of America

Naader Hasani