Matrix Semiconductor, Inc.

Candescent Technologies Corporation

Sandisk 3d LLC

Sandisk Corporation

N Johan Knall

James Montague Cleeves

Michael A Vyvoda

Christopher J Spindt

Mark G Johnson

Duane A Haven

Roy E Scheuerlein

Vivek Subramanian

John M Macaulay

Calvin K Li

John D Porter

Bendik Kleveland

Roger W Barton

Paul N Ludwig

Manish Bhatia

Thomas H Lee

Igor G Kouznetsov

Gabriela S Chakarova

Christopher John Petti

S Brad Herner

Andrew J Walker

Stephanie Jeanne Oberg

Peter C Searson

Colin D Stanners

P Michael Farmwald

Swayambu Ramani

Victoria A Bascom

Maria S Nikolova

William H Creel

Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.

Silicon nitride antifuse for use in diode-antifuse memory arrays

A high density plasma oxidation process is provided in which a dielectric film is formed having a predetermined thickness. Plasma oxidation conditions are provided such that the growth rate of the dielectric film is limited in order to produce dielectric layer having a precise thickness and uniformity. The high density plasma oxidation process can be used to fabricate gate oxide layers, passivation layers and antifuse layers in semiconductor devices such as semiconductor memory devices and multi-level memory arrays.

Process for fabricating a dielectric film using plasma oxidation

A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.

Electrically isolated pillars in active devices

A memory array having memory cells each comprising a diode and a phase change material or antifuse is reliably programmed by maintaining all word lines and bit lines connected to unselected memory cells at intermediate voltages and applying voltages to place the diode of a selected cell or cells in a reverse biased state and sufficient to program the phase change material or antifuse. Thus leakage through unselected cells is low so power wasted is small, and assurance is high that no unselected memory cells are disturbed.

Reverse-bias method for writing memory cells in a memory array

A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.

A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

Three-dimensional memory array and method of fabrication

A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.

Patterning three dimensional structures

In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.

Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells

Apparatus and method for disturb-free programming of passive element memory cells

The preferred embodiments described herein relate to an integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells arranged in L layers stacked vertically above one another in a single integrated circuit. A memory cell layer in the memory array is selected, and one of N sets of memory-cell-layer-dependent writing conditions and/or one of K sets of memory-cell-layer-dependent reading conditions is selected based on the selected memory cell layer. In another preferred embodiment, a temperature of an integrated circuit is measured, and a set of writing conditions and/or a set of reading conditions is selected based on the measured temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions

A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on insulator substrate or in a compound semiconductor substrate.

Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

A memory cell for a three-dimensional intergrated circuit memory is disclosed. The cell includes a very highly doped semiconductor regions with a doping level of 10 atoms cm or higher. An antifuse region is disposed between the heavily doped region and a more lightly doped region.

Memory cell with antifuse layer formed at diode junction

An apparatus including a circuit of n circuit levels formed over a substrate from a first level to a nth level, wherein n is greater than one, and each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing operation that is applied to more than one of the n circuit levels simultaneously. An apparatus including a circuit of a plurality of circuit levels, each of the plurality of circuit levels having substantially similar material parameters.

Growing community of inventors

Sunnyvale, CA, United States of America

N Johan Knall