International Business Machines Corporation

Quickturn Design Systems, Inc.

Cadence Design Systems, Inc.

N James Tomassetti

William F Beausoleil

Tak-kwong Ng

Helmut Roth

Peter Tannenbaum

Mitchell Grant Poplack

Edmund D Blackshear

Chon Cheong Lei

Lawrence A Thomas

Tung-Sun Tung

Jac Anders Burke

Michael Juergen Kessler

Method and apparatus for controlling power in an emulation system is described. In one example, power is controlled in a processor-based emulation system coupled to a host computer. A logic design is processed to identify unused resources in the emulation system during an emulation cycle. Power of the unused resources is controlled during emulation of a design under verification corresponding to the logic design by the emulation system. The resources may be identified as being unused during one or more steps of the emulation cycle. The power of the unused resources may be controlled by at least one of: powering down one or more of the unused resources; disabling one or more of the unused resources; freezing inputs to one or more of the unused resources; or setting inputs to one or more of the unused resources to a constant state. In this manner, power consumption of the emulation system is reduced.

Method and apparatus for controlling power in an emulation system

Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of 'cascade' connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Clustered processors in an emulation engine

A method and structure for a memory structure that includes a plurality of substrates stacked one on another is disclosed. The invention includes a plurality of connectors connecting the substrates to one another and a plurality of memory chip packages mounted on the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.

Vertically stacked memory chips in FBGA packages

Chips requiring high temperature reflow for attachment to a module substrate are attached first and then a eutectic water soluble solder paste and/or water soluble flux is dispensed on both the TSOP and the PBGA chip pads instead of using the paste screening techniques. The dispensing is done by injecting solder on the solder sites individually. Characteristics of the solder paste used is that it must be fluid enough to be injected onto the individual sites yet have enough body that it remains in place and does not run from site to site once dispensed. A paste capable of providing such characteristics is one having: a ) a very fine particle size in the range of 400 to 500 mesh and preferably between 400 and 450 mesh; b) a low viscosity (below 500 k centerpoise and preferably between 425 to 375 cps); and c) a solid content of 86% or lower and preferably between 84 and 80%. The chips to be joined to the module using low temperature module joining are then placed on the module substrate surface and then put in an oven for reflow to attach these chips to the surface. After the joining process, the modules are cleaned by spraying deionized water on them to remove any flux or solder residues and the modules are electrically tested to determine if the joining process has resulted in connection with the proper mechanical and electrical characteristics.

Assembly of multi-chip modules using eutectic solders

Growing community of inventors

Kingston, NY, United States of America

N James Tomassetti