Advanced Micro Devices Corporation

N Bruce Threewitt

Jimmy R Madewell

Aloysius T Tam

Joseph A Brcich

Roy J Levy

An integrated electronic memory circuit is provided which includes memory circuitry for storing binary data in an array of memory locations; first data signal providing circuitry for providing input data signals to the memory circuitry, for storage by the memory circuitry as binary data at respective memory locations; and write signal generator circuitry for generating a write signal causing the memory circuitry to accept input data signals from the first data signal providing circuitry for storing in the array.

Integrated electronic memory circuit with internal timing and operable

A content-addressable memory cell and memory array are disclosed. Each cell comprises a random access memory storage component and a comparison component for performing the contact addressability function. In a disclosed CMOS embodiment, a DRAM cell and an exclusive-NOR gate are combined to form the CAM cell.

High density, dynamic, content-addressable memory cell

A programmable event generator for generating digital timing waveforms in response to a triggering signal includes one programmable read-only memory for storing and outputting data words corresponding to the digital timing waveforms and next address words to address another of the data words, a storage register for temporarily storing and outputting any one of the data words and next address words, another mapping programmable read-only memory for storing and outputting starting address words to start the addressing of the one programmable read only memory, a multiplexer to select either a starting address word or a next address word to address the one programmable read-only memory, and a programmable control circuit, responsive to the triggering signal, for clocking the storage register at a programmed clock frequency.

Apparatus for generating digital timing waveforms

An improved semiconductor memory device for serial scan applications is presented. The semiconductor memory device as presented includes a main memory means combined with an on-board means for implementing a shift register function. The shift register function of the present invention is implemented by utilizing a secondary memory means in conjunction with parallel loadable, multiple-bit address counters.

Semiconductor memory device for serial scan applications

A computer system having a central processing unit, a dynamic memory controller, an error detection and correction network and a dynamic memory for storing data that are subject to being refreshed and to data bit errors. The dynamic memory controller has a refresh mode for controlling access to the memory only to refresh the data, a refresh with error detection and correction mode, for controlling access to the memory to merge or simultaneous refresh a row of data while detecting and correcting data bit errors, and a read/write mode for controlling access to the memory in response to CPU requests for a read/write memory operation.

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Fremont, CA, United States of America

N Bruce Threewitt