Samsung Electronics Co., Ltd.

Myungsun Kim

Dongsuk Shin

Hoi Sung Chung

Dong Hyuk Kim

Jongchul Park

Sangbok Han

Hyojeong Lee

Kwonsik Kim

Seyoun Lim

Jung Nyoung Heo

Seongjin Nam

Ho Young Lee

Jongho Lee

Hyunjung Kim

Seunghwan Lee

Kibeom Kim

Myungkwan Choi

Seokhyun Kim

Weonhong Kim

Moonkyun Song

Dae-Kwon Joo

Hajin Lim

Jinho Do

Jinkyu Koo

Chang-Bong Oh

Sunghyuk Kwon

Jaeun Park

Youngrae Cho

Gyeonghoon Kim

Bonghyun Cho

YongJoo Lee

According to various embodiments of the disclosure, an electronic device includes a wireless communication circuit that communicates with an external electronic device, and a processor, wherein the processor may pair the electronic device with the external electronic device by using the wireless communication circuit, obtain accessibility setting information of the external electronic device from the external electronic device, and set an accessibility feature of the electronic device based on at least a piece of the obtained accessibility setting information. In addition, it is possible to implement various embodiment understood through the disclosure.

Method for providing accessibility feature and electronic device for performing same

Disclosed is an electronic apparatus which executes an artificial intelligence algorithm using a convolution calculation unit and memory local to the electronic apparatus.

Processor, electronics apparatus and control method thereof

A hardware-based memory management apparatus and method is provided. The apparatus includes a memory allocation module, a memory reclamation module, and a memory compaction module, based on hardware to accelerate a memory manger of an operating system. The method manages memory using the memory allocation module, memory reclamation module, and memory compaction module.

Hardware-based memory management apparatus and memory management method thereof

An application execution method for improving the operation speed of the application in executing or in the middle of running the application is provided. The application execution method includes detecting a launch of an application, preloading Input/Outputs (I/Os) requested at the launch based on profile data with I/Os requested at a previous launch of the application, and updating the profile data based on at least one of the I/Os requested at current and previous launches of the application.

Apparatus and method for improving operation speed of application

Execution method and apparatus

Provided are a method and apparatus for task scheduling based on hardware. The method for task scheduling in a scheduler accelerator based on hardware includes: managing task related information based on tasks in a system; updating the task related information in response to a request from a CPU; selecting a candidate task to be run next after a currently running task for each CPU on the basis of the updated task related information; and providing the selected candidate task to each CPU. The scheduler accelerator supports the method for task scheduling based on hardware.

Apparatus and method for hardware-based task scheduling

A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Semiconductor devices and methods of fabricating the same

A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer.

Semiconductor devices including an epitaxial layer with a slanted surface

A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.

Semiconductor devices including MOS transistors having an optimized channel region and methods of fabricating the same

A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.

Methods for fabricating semiconductor devices

A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.

Semiconductor devices and methods for fabricating the same

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Hwaseong-si, South Korea

Myungsun Kim