Samsung Electronics Co., Ltd.

Myungsoo Noh

Jeonglim Kim

Dawoon Choi

Youngdeok Kwon

Sunghwan Bae

Seulki Hong

Moongì Cho

Sangwook Park

Hee Jae Jeong

Noyoung Chung

Sunghun Jung

Hyungjong Lee

Kangmin Jung

Inseop Lee

Bongkeun Kim

Provided is a layout design method including designing a preliminary layout including a source/drain contact pattern of an integrated circuit device, designing a first layout including a cut pattern for cutting the source/drain contact pattern, designing a second layout configured by excluding a pattern overlapping the pattern of the first layout from the preliminary layout, and correcting the preliminary layout by reflecting an etch skew based on at least one parameter of the second layout.

Layout design method and method of manufacturing integrated circuit device using the same

An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a device region of a substrate. A gate line extends in a second lateral direction on the fin-type active region. The second lateral direction intersects with the first lateral direction. A source/drain region is adjacent to one side of the gate line on the fin-type active region. A gate contact is on the gate line and connected to the gate line. A source/drain contact is on the source/drain region and includes a first segment facing the gate contact and a second segment integrally connected to the first segment. The second segment extends from the first segment in the second lateral direction. In the first lateral direction, a first distance from the first segment to the gate line is greater than a second distance from the second segment to the gate line.

Integrated circuit device

A semiconductor device includes a substrate; a guard ring disposed on the substrate and adjacent to an edge of the substrate; an integrated circuit structure surrounded by the guard ring and disposed on the substrate; and an insulating material structure disposed on a side surface of the guard ring, and wherein the guard ring includes a plurality of guard active structures on the substrate, a plurality of guard contact structures disposed on each of the plurality of guard active structures, and a guard interconnection structure disposed on a pair of guard contact structures adjacent to each other, among the plurality of guard contact structures, wherein each of the plurality of guard active structures includes a plurality of guard active fins spaced apart from each other.

Semiconductor device including guard rings

The present disclosure relates to a fabrication method of a photomask. The method of fabricating a photomask provides for a layout of patterns to be designed. The layout of patterns may be formed on a wafer on which chips are formed. The layout of patterns are corrected to provide a layout of a photoresist pattern serving as an etching mask for forming the patterns on the wafer while generating a flare map of the patterns. An optical proximity correction (OPC) may be performed at a chip level on the corrected layout of patterns to perform a secondary correction of the layout of patterns. A second OPC may be performed at a level of a shot which includes a plurality of ones of the chips by reflecting the flare map on the second corrected layout of patterns to a third corrected layout of patterns.

Method of fabricating a photomask

An integrated circuit device includes: a substrate including a fin type active region extending in a first direction; a gate structure intersecting the fin type active region and extending in a second direction perpendicular to the first direction; a source/drain region on sides of the gate structure; a gate isolation insulating layer contacting an end of the gate structure; a first contact connected to the source/drain region; and a second contact connected to the source/drain region, the second contact being longer in the second direction than the first contact, the second contact includes a first portion extending in the second direction from an area adjacent to one side of the gate structure beyond the end of the gate structure and facing a sidewall of the gate structure, and a second portion facing a sidewall of the gate isolation insulating layer, and the first portion is wider than the second portion.

Integrated circuit device and a method of manufacturing the same

In a method of manufacturing a photomask, a layout of a circuit mask pattern in a mask region corresponding to a chip region of a substrate is designed. A layout of a monitoring mask pattern representing a critical dimension (CD) of the circuit mask pattern in the mask region is designed. The monitoring mask pattern includes a mask-critical dimension uniformity (CDU) detection pattern configured to detect CDU in mask and a wafer-CDU detection pattern configured to detect CDU in wafer. A first optical proximity correction (OPC) is performed on the mask-CDU detection pattern. A second optical proximity correction is performed on the wafer-CDU detection pattern. A photomask having the circuit mask pattern and the monitoring mask pattern is formed.

Growing community of inventors

Suwon-si, South Korea

Myungsoo Noh