Samsung Electronics Co., Ltd.

Myungkee Chung

Hyunsoo Chung

Taewon Yoo

Younglyong Kim

Aenee Jang

Jinchan Ahn

A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.

Semiconductor package with increased thermal dissipation

A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.

Semiconductor package, and a package on package type semiconductor package having the same

Disclosed is a semiconductor package comprising a semiconductor chip and a redistribution layer. The semiconductor chip includes a semiconductor substrate, a passivation layer, and first power, second power, and signal pads exposed from the passivation layer. The redistribution layer includes a photosensitive dielectric layer, and first to third redistribution patterns and a high-k dielectric pattern that are in the photosensitive dielectric layer. The first, second, and third redistribution patterns are respectively connected to the first power, second power, and signal pads. The high-k dielectric pattern is between the first and second redistribution patterns. The photosensitive dielectric layer includes a first dielectric material. The high-k dielectric pattern includes a second dielectric material whose dielectric constant greater than that of the first dielectric material. The high-k dielectric pattern is in contact with the passivation layer. The passivation layer includes a dielectric material different from the first and second dielectric materials.

Semiconductor package

A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.

Semiconductor package and method of manufacturing the same

A semiconductor package includes a semiconductor chip including a contact pad on an active surface, a first insulating layer on the active surface including a first opening that exposes the contact pad, a redistribution layer connected to the contact pad and extending to an upper surface of the first insulating layer, a second insulating layer on the first insulating layer and including a second opening that exposes a contact region of the redistribution layer, a conductive post on the contact region, an encapsulation layer on the second insulating layer and surrounding the conductive post, and a conductive bump on an upper surface of the conductive post. The conductive post includes an intermetallic compound (IMC) layer in contact with the conductive bump. An upper surface of the IMC layer is lower than an upper surface of the encapsulation layer.

Semiconductor package with conductive bump on conductive post including an intermetallic compound layer

Semiconductor package with improved heat dissipation

A semiconductor package includes a package substrate, a lower package structure on the package substrate that includes a mold substrate, a semiconductor chip in the mold substrate having chip pads exposed through the mold substrate, spacer chips in the mold substrate and spaced apart from the semiconductor chip, and a redistribution wiring layer on the mold substrate that has redistribution wirings electrically connected to the chip pads, first and second stack structures on the lower package structure spaced apart from each other, each of the first and second stack structures including stacked memory chips, and a molding member covering the lower package structure and the first and second stack structures, wherein the mold substrate includes a first covering portion covering side surfaces of the semiconductor chip and the spacer chips, and a second covering portion covering a lower surface of the semiconductor chip.

Semiconductor package with stack structure and method of manufacturing the semiconductor package

A semiconductor package includes a bottom package and an upper redistribution layer disposed on the bottom package. The bottom package includes a substrate and a semiconductor chip disposed on the substrate. A conductive pillar extends upwardly from the substrate and is spaced apart from the semiconductor chip. A mold layer is disposed on the substrate and encloses the semiconductor chip and lateral side surfaces of the conductive pillar. The conductive pillar includes a connection pillar configured to electrically connect the substrate to the upper redistribution layer and an alignment pillar that is spaced apart from the connection pillar. The upper redistribution layer includes a redistribution metal pattern configured to be electrically connected to the connection pillar. A first insulating layer is in direct contact with a top surface of the redistribution metal pattern. A top surface of the alignment pillar is in direct contact with the first insulating layer.

A semiconductor package is provided including a first semiconductor package including a first semiconductor chip. The first semiconductor chip includes a first surface and a second surface opposite to the first surface. A second semiconductor package is disposed on the first semiconductor package. The second semiconductor package includes a second redistribution layer including a redistribution line. A second semiconductor chip is disposed on the second redistribution layer. A thermal pillar is disposed on the second redistribution layer. A heat radiator is disposed on the second semiconductor package and connected to the thermal pillar. The redistribution line is connected to the first semiconductor chip.

Growing community of inventors

Hwaseong-si, South Korea

Myungkee Chung