Samsung Electronics Co., Ltd.

Myunghun Woo

Bongyong Lee

Taehun Kim

Tae Hun Kim

Jinwoo Lee

Hyunjae Song

Garam Park

Seyun Kim

Doohee Hwang

Minkyung Bae

Jooheon Kang

Yukio Hayakawa

Seungyeul Yang

Gunwook Yoon

Dongho Ahn

Doyoon Kim

Changyup Park

Yumin Kim

Sunho Kim

Donggeon Gu

Suseong Noh

Park Garam

Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.

Variable resistance memory device and electronic device including the same

Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.

Nonvolatile memory device and operating method of the same

A semiconductor device includes a lower structure, a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction, and a channel structure in a channel hole passing through the stack structure. The channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole, the channel layer includes a first element, the variable resistance material layer includes a second element, different from the first element, oxygen, and oxygen vacancies, and the data storage material layer includes the first element, the second element, oxygen, and oxygen vacancies.

Semiconductor devices and data storage systems including the same

A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.

Vertical variable resistance memory devices and methods of operation in the same

A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

Method of fabricating a vertical semiconductor device

Vertical semiconductor device and method of fabricating the same

A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

Semiconductor devices having increased efficiency in generation of gate-induced drain leakage current without insulation deterioration and methods of operating the same

A three-dimensional semiconductor memory device may include a stack including gate electrodes sequentially stacked on a substrate and a vertical structure penetrating the stack. The vertical structure may include a vertical channel portion, a charge storing structure on an outer side surface of the vertical channel portion, and a pad. The pad may include a first pad portion disposed in an internal space surrounded by the vertical channel portion and a second pad portion provided on the first pad portion and extended onto a top surface of the charge storing structure. A portion of the first pad portion may be disposed at the same level as an uppermost electrode of the gate electrodes.

Three-dimensional semiconductor memory devices

An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.

Nonvolatile memory device, an operating method thereof, and a storage system including the nonvolatile memory device

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Suwon-si, South Korea

Myunghun Woo