Samsung Electronics Co., Ltd.

Myunggil Kang

Keunhwi Cho

Dongwon Kim

Sanghoon Lee

Woocheol Shin

Byounghak Hong

Dongsuk Shin

Seokhoon Kim

Pankwi Park

Minyi Kim

Minhee Choi

Seunghyun Song

Kang-Ill Seo

Uihui Kwon

Krishna Bhuwalka

Kyoungmin Choi

Yonghee Park

Seungkyu Kim

Youngseok Song

Ahyoung Kim

Daewon Ha

Jinkyu Kim

Junggil Yang

Junbeom Park

Soojin Jeong

Gibum Kim

Jaechul Kim

A semiconductor device includes a substrate, an active fin on the substrate, and a transistor on the active fin. The transistor includes a lower channel layer, an intermediate channel layer, and an upper channel layer sequentially stacked, and a gate structure traversing the active fin, respectively surrounding the channel layers, and including a gate dielectric and a gate electrode. The gate electrode includes a lower electrode portion between the active fin and the lower channel layer, an intermediate electrode portion between the lower channel layer and the intermediate channel layer, and an upper electrode portion between the intermediate channel layer and the upper channel layer. The gate electrode includes a work function adjusting metal element, and a content of the work function adjusting metal element in the lower electrode portion is different from that in each of the intermediate electrode portion and the upper electrode portion.

Semiconductor device including plurality of channel layers

A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

Semiconductor devices and methods of fabricating the same

Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

Resistance measuring structures of stacked devices

A semiconductor device includes a substrate including a first device region and a second device region, active regions spaced apart from each other on the substrate, having a constant width, extending in a first direction parallel to an upper surface of the substrate and including a first active region and a second active region provided on the first device region and a third active region and a fourth active region provided on the second device region, a plurality of channel layers provided on the active regions and configured to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate, gate structures provided on the substrate and extending to cross the active regions and the plurality of channel layers, and source/drain regions provided on the active regions on at least one side of the gate structures.

Semiconductor device

An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

Integrated circuit device

An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

A semiconductor device includes a first source/drain, a second source/drain isolated from direct contact with the first source/drain in a horizontal direction, a channel extending between the first source/drain and the second source/drain, a gate surrounding the channel, an upper inner spacer between the gate and the first source/drain and above the channel, and a lower inner spacer between the gate and the first source/drain and under the channel, in which the channel includes a base portion extending between the first source/drain and the second source/drain, an upper protrusion portion protruding upward from a top surface of the base portion, and a lower protrusion portion protruding downward from a bottom surface of the base portion, and a direction in which a top end of the upper protrusion portion is isolated from direct contact with a bottom end of the lower protrusion portion is oblique with respect to a vertical direction.

Semiconductor devices

A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

Resistor with doped regions and semiconductor devices having the same

An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1−xGex layer, where x≠0, and the inner blocking layer including a Si layer.

A semiconductor device including an active structure on a substrate, the active structure including silicon germanium patterns and silicon patterns alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on sidewalls of the active structure that face in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source/drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction that is perpendicular to the first direction, wherein the silicon germanium patterns are silicon rich-silicon germanium.

Method for manufacturing a semiconductor device

A resistor includes a substrate including an active region protruding from an upper surface of the substrate and extending in a first horizontal direction, a doped region extending in the first horizontal direction on the active region and comprising a semiconductor layer with n-type impurities, a plurality of channel layers spaced apart from each other in a vertical direction on the active region and connected to the doped region, a first gate electrode and a second gate electrode extending in the second horizontal direction intersecting the first horizontal direction and surrounding the plurality of channel layers, a first contact plug and a second contact plug in contact with an upper surface of the doped region. The first contact plug is adjacent to the first gate electrode. The second contact plug is adjacent to the second gate electrode.

Resistor with doped regions

Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).

An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a SiGelayer, where x&#x2260;0, and the inner blocking layer including a Si layer.

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Suwon-si, South Korea

Myunggil Kang