Samsung Electronics Co., Ltd.

Myung-Yoon Um

Jung-Gun You

Gi-Gwan Park

Se-wan Park

Young-Joon Park

Baik-Min Sung

Jeong-Hyo Lee

Ji-Yong Ha

Jun-sun Hwang

Jae-yup Chung

Dong-Ho Cha

Sug-Hyun Sung

Ki-il Kim

Sang-Won Kim

Geum-Jong Bae

In-Wook Cho

Hyung-Dong Kim

Byoung-jin Lee

Jin-hee Kim

Geon-Woo Park

Myoung-Kyu Seo

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.

Semiconductor devices having gate structures with skirt regions

A semiconductor device is provided. The semiconductor device includes a field insulating film on a substrate, a first fin type pattern which is formed on the substrate and protrudes upward from an upper surface of the field insulating film, and a gate electrode which intersects with the first fin type pattern on the field insulating film and includes a first portion and a second portion, the first portion being located on one side of the first fin type pattern and including a first terminal end of the gate electrode, and the second portion being located on the other side of the first fin type pattern, wherein a height from the substrate to a lowest part of the first portion is different from a height from the substrate to a lowest part of the second portion.

Semiconductor device

An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.

Integrated circuit device

A semiconductor device is provided. The semiconductor device may include a field insulating film on a substrate, a first fin type pattern which is formed on the substrate and protrudes upward from an upper surface of the field insulating film, and a gate electrode which intersects with the first fin type pattern on the field insulating film. The gate electrode may include a first portion and a second portion, the first portion being located on one side of the first fin type pattern and including a first terminal end of the gate electrode, and the second portion being located on the other side of the first fin type pattern. A height from the substrate to a lowest part of the first portion may be different than a height from the substrate to a lowest part of the second portion.

Integrated circuit device and method of manufacturing the same

A method of fabricating a semiconductor device includes forming a plurality of mask patterns comprising a real mask pattern and a dummy mask pattern on a substrate, removing the dummy mask pattern and etching the substrate using the real mask pattern as a mask to form a first trench, a second trench, and a fin-type pattern defined by the first trench and the second trench. The second trench contacting the fin-type pattern comprises a smooth pattern which is convex and positioned between a bottom surface and a side surface of the second trench, a first concave portion which is positioned between the side surface of the second trench and the smooth pattern, and a second concave portion which is positioned between the convex portion and the bottom surface of the second trench.

Semiconductor device and method for fabricating the same

A semiconductor device includes a substrate including a first trench, a first fin pattern on the substrate that is defined by the first trench, a gate electrode on the substrate, and a field insulating layer on the substrate. The first fin pattern includes an upper part on a lower part. The first fin pattern includes a first sidewall and a second sidewall opposite each other. The first sidewall is concave along the lower part of the first fin pattern. The second sidewall is tilted along the lower part of the first fin pattern. The field insulating layer surrounds the lower part of the first fin pattern. The gate electrode surrounds the upper part of the first fin pattern.

Erasure methods for a nonvolatile memory cell that includes a gate electrode on a substrate, source and drain regions in the substrate at respective sides of the gate electrode, and a charge storage layer interposed between the gate electrode and the substrate. A nonzero first voltage is applied to the source region starting at a first time. While continuing to apply the first nonzero voltage to the source region, a second voltage having an opposite polarity to the first voltage is applied to the gate electrode starting at a second time later than the first time. The second voltage may increase in magnitude, e.g., stepwise, linearly and/or along a curve, after the second time.

Soft erasing methods for nonvolatile memory cells

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Seoul, South Korea

Myung-Yoon Um