Skhynix Inc.

Hynix Semiconductor Inc.

Myung Su Kim

Sam Kyu Won

Jae Won Cha

Sang Kyu Lee

Wan Ik Cho

Dong Wook Lee

Sung Hoon Cho

Gil Bok Choi

Min Ho Her

Hwang Huh

Min Sang Park

Kang Woo Park

Yun Bong Lee

Beom Seok Hah

Suk Kwang Park

Seung Jae Chung

Sang Jo Lee

Seong Uk Kim

Chang Jin Sunwoo

Provided herein are a memory system and a method of programming the same. The memory system may include a memory device including memory cells for storing data and a plurality of latches for storing code values indicating the data. The memory device may be configured to program data into each of the memory cells, store an original code value indicating the data in the plurality of latches, and change the original code value stored in the plurality of latches to an erase code value in response to a verification pass, and a memory controller configured to output, to the memory device, a suspend command for suspending at least the programming in response to detecting a sudden power-off and a recovery command for restoring a code value changed to the erase code value.

Memory system restoring changed data and method of programming the same

A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

Semiconductor device and operating method thereof

A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Semiconductor memory device and operating method thereof

Disclosed are a memory system, a semiconductor memory device and a method of operating the same. The memory system includes: a memory controller to output a command, address and data; and a semiconductor memory device to store at least one page data in each memory cell in response to the command, the address and the data, the memory controller to separately output first address used for determining the at least one page data from the data and second address used for determining a word line coupled to at least one memory cell.

Memory system, semiconductor memory device and operating method thereof

A semiconductor device comprises a memory cell array comprising memory cells coupled to word lines and bit lines, a voltage generator suitable for generating a drive voltage to be applied to a selected word line, and a control logic suitable for detecting the number of pulses of a program voltage received from the memory cell array in a program operation, storing bias information corresponding to the detected number of pulses in a register, and controlling a level of the program voltage for a subsequent program operation based on the bias information.

Semiconductor device and method for operating the same

A method of operating a semiconductor device includes storing a supplying condition of a read voltage inputted from an external source into an internal register to perform a read operation of memory cells, performing the read operation repetitively with changing levels of the read voltage according to the supplying condition of the read voltage in the event that the number of error bits in a data read from the memory cells exceeds an allowable range, and storing an iteration number of the read operation in the internal register in case the number of the error bits falls within the allowable range.

Semiconductor device and method of operating the same

A semiconductor integrated circuit includes a memory cell area comprising a main cell and a spare cell, and a memory controller configured to set an offset value using a program verify level which is set during a program operation, and set a read level using the offset value during a read operation.

Semiconductor integrated circuit and data read method

A nonvolatile memory device includes first and second registers configured to store parameters received via an input/output (IO) unit, a microcontroller configured to control an operation of the nonvolatile memory device according to the parameter stored in the first register, and a control logic unit configured to, when a parameter is received via the IO unit while the microcontroller performs an internal operation, store the received parameter in the second register.

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Gyeonggi-do, South Korea

Myung Su Kim