Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Myung-Soo Jang

Jong-Wha Chong

Cheol-Jon Jang

Jae-Hwan Kim

Hyo-Sig Won

Hyoun-Soo Park

Jae-Rim Lee

Da-Yeon Cho

Ji-Ho Song

Min-Beom Kim

Kyung-In Cho

Byung-Gyu Ahn

Wen Rui Li

A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks. A space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.

Computing system for performing colorless routing for quadruple patterning lithography

A computer-implemented method compresses placing standard cells based on design data defining an integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which a first pattern, a second pattern, and a third pattern in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a non-transitory computer-readable storage medium. The space constraints define minimum spaces between the first pattern, the second pattern, and the third pattern. A color violation does not occur between the first pattern, second pattern, and the third pattern. A first mask, a second mask, and a third mask are generated based on the layout. A semiconductor device is manufactured by using the generated first mask, the second mask, and the third mask.

Integrated circuit, and computing system and computer-implemented method for designing integrated circuit

A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die parallel to the first die. The method also includes determining a first bound region. The first bound region includes a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die. The method additionally includes calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.

Method of manufacturing semiconductor device

To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal.

Method of designing power supply network

A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.

Method of designing arrangement of TSV in stacked semiconductor device and designing system for arrangement of TSV in stacked semiconductor device

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Seoul, South Korea

Myung-Soo Jang