Samsung Electronics Co., Ltd.

Myung Kyu Lee

Jun Jin Kong

Ki Jun Lee

Dae Hyun Kim

Beom Kyu Shin

Jin-Hoon Jang

Sung-Rae Kim

Yeong Geol Song

Yong Gyu Chu

Sung Hye Cho

Hong Rak Son

Pil Sang Yoon

Kwang Hoon Kim

Ung Hwan Kim

Geun Yeong Yu

A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Memory device and memory system including the same

Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Semiconductor memory device, controller, memory system, and operation method thereof

A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.

Data storage system

Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Semiconductor memory device, controller, and memory system

A method of decoding data of a non-volatile memory device is provided. The method includes a first decoding operation of reading first hard decision data from the non-volatile memory device using a first hard decision read level and performing decoding using the first hard decision data; a second decoding operation of reading first soft decision data from the non-volatile memory device when the decoding fails in the first decoding operation, and performing decoding using the first soft decision; and a third decoding operation of changing from the first hard decision read level to a second hard decision read level when the decoding fails in the second decoding operation, reading second hard decision data using the second hard decision read level, and performing decoding either using the second hard decision data or using both the second hard decision data and the first soft decision data.

Data decoding method of non-volatile memory device and apparatus for performing the method

Growing community of inventors

Seoul, South Korea

Myung Kyu Lee