Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Lg Information & Communications, Ltd.

Myung-Kyu Lee

Ki-Jun Lee

Jun Jin Kong

Jun-Jin Kong

Dong-Min Shin

Dae-Hyun Kim

Kyeong-Cheol Yang

Hong-Rak Son

Yong-Gyu Chu

Beom-Kyu Shin

Young-Jun Hwang

Geun-Yeong Yu

Sung-Hye Cho

Hong-Sil Jeong

Hyun-Koo Yang

Seho Myung

Jae-Hong Kim

Seung-Chan Lim

Se-Jin Lim

Eun-cheol Kim

Ung-hwan Kim

Ji-Youp Kim

Jong-Ha Kim

A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Semiconductor memory devices and memory systems including the same

An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.

Error correcting circuit performing error correction on user data and error correcting method using the error correcting circuit

An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.

Error correction code circuits, semiconductor memory devices and memory systems

An error correction code (ECC) decoder of a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection/correction circuit. The ECC checker generates characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array. The syndrome generator outputs a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix. The an error detection/correction circuit generates a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.

Error correction code decoders, semiconductor memory devices and memory systems

A method and system of recovering data includes reading reference codewords, which have code correlation with a target codeword, from a memory device when an error-correcting code (ECC) decoding process for a decoder input of the target codeword has failed. A decoder input of a corrected target codeword is generated based on an operation process using the target codeword and the reference codewords. An ECC decoding process is performed again on the decoder input of the corrected target codeword.

Method of recovering data and memory system and raid storage system using the same

A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

Method of decoding low density parity check (LDPC) code, decoder and system performing the same

A list decoding method for a polar code includes generating a tree-type decoding graph for input codeword symbols; the generating a tree-type decoding graph including, generating a decoding path list to which a decoding edge is added based on a reliability of a decoding path, the decoding path list being generated such that, among decoding paths generated based on the decoding edge, decoding paths within a threshold number of critical paths survive within the decoding path list in an order of high likelihood probability, and determining an estimation value, which corresponds to a decoding path having a maximum likelihood probability from among decoding paths of the decoding path list, as an information word.

List decoding method for polar code and memory system using the same

A method of estimating a deterioration state of a memory device comprises reading data from selected memory cells connected to a selected wordline of a memory cell array by applying to the selected wordline a plurality of distinct read voltages having values corresponding to at least one valley of threshold voltage distributions of the selected memory cells, generating quality estimation information indicating states of the threshold voltage distributions using the data read from the selected memory cells, and determining a deterioration state of a storage area including the selected memory cells based on the generated quality estimation information.

Method of estimating deterioration state of memory device and related method of wear leveling

An apparatus and method for compensating for phase noise in a receiver supporting Orthogonal Frequency Division Multiplexing (OFDM) by receiving a frequency-domain recovered signal and a time-domain received signal, estimating an average phase noise for each of the partial blocks of the signals, calculating an overall average phase noise using the average phase noises of the partial blocks, and removing the phase noise from the time-domain received signal using the calculated total average phase noise.

Apparatus and method for compensating for phase noise in a receiver supporting OFDM

The present invention provides a terminal adapter for BISDN. The terminal that is applicable to both variable bit rate (VBR) ATM cells and constant bit rate (CBR) ATM cells for connecting a S point to a R point. The terminal adapter can transfer and prioritize CBR and VBR ATM cells. The system uses a multiplexer/demultiplexer that is capable of determining an ATM cell type and capable of determining a priority of ATM cell types. The mumiplexer/demultiplexer determines priority among ATM cells and selects ATM cells among the both of VBR ATM cells and CBR ATM cells, and outputs the selected ATM cells to the said physical layer according to the determined priority when transmitting data from R point to S point, or determines the type of ATM cell, and outputs VBR ATM cells to the ATM AAL3/4,5 layer, CBR ATM cells to one of the multiple CBR interfaces when transmitting data from S point to R point.

Growing community of inventors

Seoul, South Korea

Myung-Kyu Lee