Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Myung-Koo Hur

Sung-Man Kim

Chi-Woo Kim

Chang-Oh Jeong

Mun-Pyo Hong

Hong-Woo Lee

Yang-Sun Kim

Young-Jae Tak

Chun-Gi You

Jang-Soo Kim

Jong-Hwan Lee

Beom-jun Kim

Hyang-Shik Kong

Seong-Young Lee

Bong-Jun Lee

Dong-Gyu Kim

Jae-Ho Lee

Jong-Woong Chang

Yong Woo Lee

Hee-Joon Kim

Sang-Gun Choi

Myung-Jae Park

Jin-Suk Seo

Yeon-Kyu Moon

Jong-Oh Kim

Myung-Sub Lee

Gyu-Tae Kim

Jong-Hyuk Lee

Chang-Ho Lee

Jang-Kun Song

Seung-Hwan Moon

Beohm-Rock Choi

Na-Young Kim

June-Woo Lee

Cheol-Gon Lee

Yu-Jin Kim

Ki-Nyeng Kang

Joo-han Kim

Hyun-Been Hwang

Hyeong-Jun Park

Shin-Tack Kang

Yeo-Geon Yoon

Jung-Suk Bang

Woo-Sik Jun

Dae-Woo Kim

Soo-Beom Jo

Dong-Wuuk Seo

Sun-Ok Song

Jin-A Lee

Beom-Jun Kim

Chua-Gi You

Jueng-Gil Lee

Sung-Mau Kim

An organic light emitting display device includes a substrate, a gate insulation layer, a planarization layer, a boundary pattern, and a sub-pixel structure. The substrate includes a sub-pixel region and a transparent region. The gate insulation layer is disposed on the substrate. The planarization layer is disposed in the sub-pixel region on the gate insulation layer, and exposes the transparent region. The boundary pattern covers a boundary of the sub-pixel region and the transparent region. The sub-pixel structure is disposed on the planarization layer.

Organic light emitting display device

A gate driving circuit including a plurality of stages connected with each other and configured to output a plurality of gate signals. An n-th (n is a natural number) stage including a gate output part including a first transistor connected between a clock signal and an output node outputting an n-th gate signal, the first transistor having a gate electrode connected to a control node, a carry part connected between the clock signal and a carry node outputting an n-th carry signal, a first node control part connected between the output node and a first low voltage, and a second node control part including at least one transistor connected between the control node and a second low voltage different from the first low voltage.

Gate driving circuit and display apparatus having the same

A gate driving circuit is provided which includes a plurality of stages cascade-connected with each other and outputting a plurality of gate signals. An n-th (n is a natural number) stage includes a gate output part, a first node control part and a carry part. The gate output part includes a first transistor. The first transistor outputs a high voltage of a clock signal to a high voltage of an n-th gate signal in response to a high voltage of a control node. The first node control part is connected to the control node to control a signal of the control node and includes at least one transistor having a channel longer than the channel length of the first transistor. The carry part outputs the high voltage of the clock signal to an n-th carry signal in response to the signal of the control node.

An organic light-emitting display device includes a plurality of emission pixels aligned in columns and rows, each of the emission pixels including an emission device and a first pixel circuit coupled to the emission device, a dummy pixel including a second pixel circuit in each column of the emission pixels, and a repair line in each column, wherein a same data signal is provided to one of the emission pixels coupled to the repair line and to the dummy pixel coupled to the repair line, and wherein the emission pixels are configured to simultaneously emit light.

Organic light-emitting display device, method of repairing the same, and method of driving the same

An organic light emitting display apparatus includes a pixel part including a pixel electrode, a light emitting layer and an opposite electrode, and a contact part in which the opposite electrode contacts a power line, wherein a first thickness of the opposite electrode in the pixel part is different from a second thickness of the opposite electrode in the contact part.

Organic light emitting display apparatus and manufacturing method thereof

A gate driving circuit and a display device having the same, a pull-up unit pulls up a current gate signal by using a first clock signal during a first period of one frame. A pull-up driver coupled to the pull-up unit receives a carry signal from one of the previous stages to turn on the pull-up unit. A pull-up unit receives a gate signal from one of the next stages, discharges the current gate signal to an off voltage level, and turns off the pull-up unit. A holder holds the current gate signal at the voltage level. An inverter turns on/off the holder in response to a first clock signal. A ripple preventer has a source and a gate coupled in common to an output terminal of the pull-up unit and a drain coupled to an input terminal of the inverter, and includes a ripple preventing diode for preventing a ripple from being applied to the inverter.

Gate driving circuit having improved tolerance to gate voltage ripple and display device having the same

A display substrate includes a pixel electrode, an m-th data line ('m' is a natural number), a floating electrode, a (m+1)-th data line and a storage electrode. The pixel electrode is disposed in a pixel area of the substrate. The m-th data line is disposed at a first side of the pixel electrode and electrically connected to the pixel electrode. The floating electrode partially overlaps with the m-th data line. The (m+1)-th data line is disposed at a second side of the pixel electrode. The storage electrode is spaced apart from the (m+1)-th data line.

Display substrate, method of manufacturing the same, and display apparatus having the same

A thin-film transistor array panel and a manufacturing method thereof are provided for one or more embodiments. The thin-film transistor array panel may include: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a source electrode and a drain electrode formed on the gate insulating layer; and a flatness layer formed on the source electrode and the drain electrode, wherein the drain electrode has a higher height than the flatness layer.

Thin-film transistor array panel and method of fabricating the same

In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.

Array substrate having increased inspection efficiency and display apparatus having the same

Disclosed is a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer interposed there between. The first substrate is provided with gate lines and data lines thereon. The gate lines and data lines cross with each other and are insulated from each other. Pixel electrodes are stacked on the gate lines and data lines. Each pixel electrode includes first and second sub-pixel electrodes spaced apart from each other and a connection electrode, which connects the first sub-pixel electrode to the second sub-pixel electrode. The second substrate is provided with a common electrode thereon. The common electrode includes a first domain divider formed on the center of the first sub-pixel electrode and a second domain divider formed on the center of the second sub-pixel electrode.

Liquid crystal display device

A display apparatus has a pixel including a main pixel connected to a main gate line and a data line, and a sub-pixel connected to a sub-gate line and the data line. A main gate driver outputs a main gate pulse to the main gate line during a time periodH. A sub-gate driver receives the main gate pulse and outputs a sub-gate pulse to the sub-gate line during a first portion of time periodH. The data driver applies a sub-pixel voltage to the data line during the first portion of time periodH and applies the main pixel voltage to the data line during a second portion of time periodH.

Display apparatus

A gate driver comprises a shift register that has a plurality of stages connected together and outputs a gate signal comprising a first pulse and a second pulse to a gate line. A stage includes a holding part, a pre-charging part, a pull-up part, and a pull-down part. The holding part discharges an output terminal to an off-voltage in response to a first clock signal. The pre-charging part turns off the holding part and outputs the first clock signal as the first pulse to the output terminal in response to an output signal of a previous stage. The pull-up part outputs a second clock signal as the second pulse to the output terminal in response to the output signal of the previous stage. The pull-down part discharges the first output terminal to the off-voltage in response to an output signal of a next stage.

Gate driver and display apparatus having the same

A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Contact structure of conductive films and thin film transistor array panel including the same

A gate driving circuit includes stages connected in series. In a stage, a pull-up part pulls up a present gate signal to a level of a first clock signal, and a pull-down part receives a next gate signal from a next stage to discharge the present gate signal to an off-voltage. A pull-up driving part turns on or turns off the pull-up part and the carry part. A holding part holds the present gate signal at the off-voltage and a present inverter turns on or turns off the holding part in response to the first clock signal. A ripple preventing capacitor is connected between a present node and an output terminal of a previous stage's inverter to prevent a ripple at the present Q-node in response to an output signal from the previous inverter.

Growing community of inventors

Cheonan-si, South Korea

Myung-Koo Hur