Skhynix Inc.

Myung Jin Jo

Dae Sung Kim

Wan Je Sung

Soon Young Kang

Kwang Hyun Kim

Ie Ryung Park

Bo Seok Jeong

Jae Young Han

A memory system includes at least one memory chip including first information regarding internal configurations and operational characteristics, and a memory controller configured to perform a data input/output operation on the at least one memory chip. The memory controller includes a core-processor engaged with firmware configured to generate at least one first command for controlling an operation associated with the first information, a memory control sequence generator configured to generate at least one second command for controlling an operation performed on a memory chip which includes second information, and a core interface configured to, when the first information is included in the second information, handover, to the core-processor from the memory control sequence generator, a process for generating some of the at least one command associated with a part of the first information, the part not included in the second information.

Low-power memory system and memory controller with compatibility and an operation method thereof

A controller controls an operation of a semiconductor memory device based on a request received from a host. The controller includes a host interface, a first function block, a second function block, and an internal command cache. The host interface generates a first internal command in response to the request. The first function block generates a second internal command in response to the first internal command. The second function block operates in response to the second internal command. The internal command cache caches at least one internal command corresponding to a reference internal command.

Controller and method of operating the same

Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.

Error correction decoder, error correction circuit having the same, and method of operating the same

The present technology includes a controller and a memory system including the same. The controller includes a memory interface configured to receive a codeword from a memory device, and an error correction circuit configured to: perform an error correction decoding operation on the codeword received from the memory interface, compare a number of unsatisfied check nodes (UCNs) detected in the error correction decoding operation with a reference number, perform or stop the error correction decoding operation on the codeword according to a result of comparing the number of UCNs and the reference number, and output a retransmission request signal of the codeword to the memory interface in response to the result, wherein the memory interface requests the codeword to the memory device in response to the retransmission request signal.

Controller and memory system having the controller

A memory system performs Error Correcting Code (ECC) decoding on data read from a plurality of target memory cells of a memory device, determines whether to update a read bias used in read operations of the memory device according to results of the ECC decoding, and then may update a value of the read bias based on result data produced by the ECC decoding and the number of data bits corrected by the ECC decoding, thereby optimizing the read bias value according to a change in a threshold voltage distribution of the memory cell, and increasing the likelihood of success of the ECC decoding.

Memory system, memory controller, and method of operating memory system

Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.

Error correction decoder

There are provided an error correction decoder and a memory system having the same. The error correction decoder includes a node processor for performing at least one iteration of an error correction decoding based on at least one parameter used for an iterative decoding, a reliability information generator for generating reliability information corresponding to a current iteration upon a determination that the error correction decoding corresponding to the current iteration has been unsuccessful, and a parameter adjuster for adjusting the at least one parameter upon a determination that the reliability information satisfies a predetermined condition, and controlling the node processor to perform a next iteration based on the adjusted.

Error correction decoder and memory controller having the same

An error correction device includes: a plurality of variable node units each configured to: receive a hard decision bit and a channel reliability value having a first bit-precision; and perform an iteration of a decoding operation on the hard decision bit based on the channel reliability value; a plurality of check node units each configured to: receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; and transmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto, wherein, during the iteration, each of the plurality of variable node units further: receives one or more first check reliability values from one or more check node units coupled thereto among the plurality of check node units; and updates the hard decision bit with reference to the channel reliability value and the one or more first check reliability values by upsizing the first bit-precision of the channel reliability value and the second bit-precision of the one or more first check reliability values.

Growing community of inventors

Gyeonggi-do, South Korea

Myung Jin Jo