Samsung Electronics Co., Ltd.

Myung-Ho Kim

Kang-Ho Byun

Hyun-Soon Jang

Si-Yeol Lee

Yun-Ho Choi

Jihyun Kim

Chang-Hyun Kim

Ho-cheol Lee

Tae-jin Kim

Churoo Park

Seung-Hun Lee

Jaehwan Kim

Dohoon Kim

Seung-hun Lee

Woong-Il Choi

Sunyong Kim

Ji-Hoon Jung

Jae-Seok Park

Chull-Soo Kim

Seung Woo Park

Jongwon Seo

Yonghak Kim

Minseo Kang

Sujeong Lim

An-Ki Cho

Young-ho Ryu

Provided are an electronic device, a method thereof, and a server. The electronic device includes a display, a communication interface, at least one processor, and a memory electrically connected to the processor, wherein, upon execution, the memory is configured to store instructions that enable the at least one processor to detect that a call event associated with another electronic device occurs; obtain call-related information associated with the another electronic device; detect at least one piece of information corresponding to a call state with the another electronic device from the obtained call-related information; and control the display to display a screen including the at least one piece of detected information and information indicating the call state with the another electronic device. Other embodiments may be possible.

Electronic device for displaying call-related information and operation method thereof

A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Multi-bank dynamic random access memory devices having all bank precharge capability

Circuit in a semiconductor memory for programming operation modes of the

Synchronous dram having a plurality of latency modes

System for selecting one of a plurality of memory banks for use in an

Semiconductor memory having a plurality of I/O buses

A semiconductor memory device for alternately selecting two groups of input/output lines according to a predetermined column address. A first group of a number of the input/output line pairs is driven by activation of any one of the selection signals within the first group, and a second group of a number of the input/output line pairs is driven by activation of any one of the selection signals within the second group. Furthermore, the input/output line pairs within the second group are precharged and equalized when the input/output line pairs within the first group are driven, and the input/output line pairs within the first group are precharged and equalized when the input/output line pairs within the second group are driven.

Semiconductor memory device having a structure for driving input/output

A bit-line sensing control circuit includes a first circuit for activating a word line and a bit line associated with a first block of a memory cell array in response to a first initial activating clock. A delay circuit generates a second initial activating clock from the first initial activating clock a predetermined period after the first initial activation clock. A second circuit for activating a word line and a bit line associated with a second block of the memory cell array is initiated in response to the second initial activating clock. Because the second block of memory cells are sensed after the first block of memory cells, spike noise related problems are substantially avoided.

Bit line sensing control circuit for a semiconductor memory device

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Suwon, South Korea

Myung-Ho Kim