Hynix Semiconductor Inc.

Skhynix Inc.

Hyundai Electronics Industries Co. Ltd.

Cj Cheiljedang Corporation

Myung Geun Park

Ki Jun Kim

Woong Hee Lee

Seong Cheol Kim

Hyung Gil Baik

Yoon Hwa Choi

Nam Soo Lee

Chang Jun Park

Ji Young Kim

Ji Eun Kim

Sang Min Park

Jin Sook Chang

In Chul Hwang

Jong Hyun Nam

Hye Min Park

Cheol Ho Joh

Il Hwan Cho

Eun Hye Do

Si Han Kim

Sung Ho Hyun

Jung Woon Choi

Sang Young Bae

The present disclosure relates to strains ofgenus, including a high content of polyunsaturated fatty acids, and a method of producing a biomass using the same. According to the novel CJM01 microalgae ofgenus of the present disclosure, the content of lipids in the biomass and the content of unsaturated fatty acid such as docosahexaenoic acid in the biomass are high, so that the microalgae itself, a biomass produced by the culturing and fermentation of microalgae, a condensate of the biomass, and a dried product of the biomass are very useful as a feed composition.

Microalgal strains ofgenus, and method of producing polyunsaturated fatty acids using the same

A semiconductor package may be provided. The semiconductor package may include a substrate formed with one or more connection pads. The semiconductor package may include a semiconductor device including at least one bump. The semiconductor package may include an anisotropic conductive fabric including conductive fibers and configured to electrically couple the at least one connection pad to the at least one bump.

Semiconductor package including a conductive fabric

A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.

Stack package

The present invention relates to a substrate for a semiconductor package and a semiconductor package having the same. A substrate for a semiconductor package includes a substrate body; a contact pad group including a plurality of contact pads parallely arranged at a determined interval on a surface of the substrate body; dummy contact pads arranged at both sides of the contact pad group, respectively; and solder resist patterns covering the substrate body and having openings exposing the dummy contact pads and the contact pad group. When bumping the semiconductor chip having the bumps to the solders arranged on the contact pads formed on the substrate, the bumping defect caused due to different volumes of each solder can be prevented.

Substrate for semiconductor package with improved bumping of chip bumps and contact pads and semiconductor package having the same

A semiconductor package includes a semiconductor chip having a first surface, a second surface located opposite the first surface, and side surfaces connecting the first and second surfaces. The semiconductor chip includes bonding pads disposed on the first surface and having a molding member formed to cover the first surface of the semiconductor chip. The molding member is formed so as to expose the side surfaces of the semiconductor chip. The semiconductor chip also includes bonding members having first ends electrically connected to the respective bonding pads and second ends that are connected to and opposite the first ends. The second ends are exposed from side surfaces of the molding member after passing through the molding member so as to allow various electrical connections.

Semiconductor package requiring reduced manufacturing processes

A printed circuit board and a flip chip package using the same are designed to minimize thermal stress due to different thermal coefficients present in areas having metal lines and solder resist versus other areas on the printed circuit board. The printed circuit board includes an insulation layer; a first metal line formed on one surface of the insulation layer and having at one end thereof a bump land and a projection which integrally extends from the bump land; a second metal line formed on the other surface of the insulation layer and having at one end thereof a ball land; a via metal line formed through the insulation layer to connect the first and second metal lines to each other; and solder resists formed on the upper and lower surfaces of the insulation layer to expose the bump land and the ball land.

Printed circuit board and flip chip package using the same with improved bump joint reliability

A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.

Flip chip package and method for manufacturing the same

A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist is performed to be removed together with a solder resist part applied on the scribe line in order to reduce an early warpage of the strip level substrate.

Method for manufacturing strip level substrate without warpage and method for manufacturing semiconductor package using the same

The stack type package module includes a plurality of stacked tape carrier packages. Each package has an elongated lead having an extension end connected to the first lateral end connected to a central portion connected to a second lateral end. The second lateral end is connected to the respective chip via a bump. The packages made as such are then stacked on top of each other on a printed circuit board. The plurality of the stacked first lateral ends are then cut and soldered the printed circuit board. The predetermined portions of the packages including the cut first lateral ends are sealed for protection.

Stack type package module and method for manufacturing the same

The stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding-pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame by utilizing a conductive adhesive material. A connecting hole is formed in the outer end of the inner lead for better electrical connection when soldered. The entire resultant structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.

Method for fabricating stacked chip package device

The present invention relates to a stack package, as well as a method for fabricating the same, the stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame. The entire structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.

Growing community of inventors

Seoul, South Korea

Myung Geun Park