International Business Machines Corporation

Mysore Sathyanaranyana Srinivas

William A Maron

Diane Garza Flemming

Hong Lam Hua

Robert H Bell, Jr

Wen-Tzer Thomas Chen, Jr

Vaijayanthimala K Anand

Octavian Florin Herescu

Greg Robert Mewhinney

Basu Vaidyanathan

David Blair Whitworth

Andrew Dunshea

Jos Manuel Accapadi

Ram Raghavan

Men-Chow Chiang

Bruce Gerard Mealey

Randal Craig Swanberg

Satya Prakash Sharma

Steven R Kunkel

Mark Elliott Hack

Suresh Eswara Warrier

Mark Robert Funk

Agustin Mena, Iii

Ronald Dean Young

Bret Ronald Olszewski

Mathew Accapadi

Calvin Lui Sze

Sandy K Kao

Donald Ray Stence

Matthew Accapadi

David William Mehaffy

Nasr-Eddine Walehiane

According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes assigning to a first set of virtual resources associated with a virtual machine a first priority and assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority. An operating system of the virtual machine is provided with the first and second priorities assigned to the respective first and second sets of virtual resources. The operating system dispatches to process a workload the virtual resources from the first set before dispatching the virtual resources from the second set.

Hybrid virtual machine configuration management

A system and method adjust instruction dispatch in a multi-pipeline processor core having a plurality of execution units for improved performance of out-of-order execution of instructions. A dispatch adjust circuit receives a queue full signal from one or more of the execution queues that indicates the corresponding execution queue is full. In response to the queue full signal, the instruction dispatch circuit sends a stop signal to the instruction issuer to stop issuing additional instructions to the queues until one or more of the queues are empty. The dispatch adjust circuit may also receive a queue empty signal from the queues to detect when they are empty to send a start signal to the issuer.

Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor

According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes: assigning to a first set of virtual resources associated with entitled resources of a virtual machine a first priority; assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; mapping the first set of virtual resources to a first physical resource of a pool of shared physical resources allocatable to the first and second sets of virtual resources, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocating the first physical resource to the first set of virtual resources.

According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied.

Performance-driven cache line memory access

According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving, a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied.

Some embodiments of the inventive subject matter are directed to operations that include determining that an access request to a computer memory results in a cache miss. In some examples, the operations further include determining an amount of cache resources used to service additional cache misses that occurred within a period prior to the cache miss. Furthermore, in some examples, the operations further include servicing the access request to the computer memory based, at least in part, on the amount of the cache resources used to service the additional cache misses within the period prior to the cache miss.

Dynamic prioritization of cache access

A data processing system includes physical computing resources that include a plurality of processors. The plurality of processors include a first processor having a first processor type and a second processor having a second processor type that is different than the first processor type. The data processing system also includes a resource manager to assign portions of the physical computing resources to be used when executing logical partitions. The resource manager is configured to assign a first portion of the physical computing resources to a logical partition, to determine characteristics of the logical partition, the characteristics including a memory footprint characteristic, to assign a second portion of the physical computing resources based on the characteristics of the logical partition, and to dispatch the logical partition to execute using the second portion of the physical computing resources.

Assigning a first portion of physical computing resources to a first logical partition and a second portion of the physical computing resources to a second logical portion

A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

Performance of emerging applications in a virtualized environment using transient instruction streams

Dynamically assigning a portion of physical computing resource to logical partitions based on characteristics of executing logical partitions

A computer implemented method includes determining first characteristics of a first logical partition, the first characteristics including a memory footprint characteristic. The method includes assigning a first portion of a first set of physical computing resources to the first logical partition. The first set of physical computing resources includes a plurality of processors that includes a first processor having a first processor type and a second processor having a second processor type. The first portion includes the second processor. The method includes dispatching the first logical partition to execute using the first portion. The method includes creating a second logical partition that includes the second processor and assigning a second portion of the first set of physical computing resources to the second logical partition. The method includes dispatching the second logical partition to execute using the second portion.

A system and technique for hybrid virtual machine configuration management includes a processor and executable logic to: assign to a first set of virtual resources associated with a virtual machine a first priority, the first set associated with entitled resources for the virtual machine; assign to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; map the first set to a first physical resource of a pool of shared physical resources, the pool of shared physical resources allocatable to the first and second sets, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocate the first physical resource to the first set of virtual resources.

A data processing system and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

Performance in predicting branches

A method, apparatus, and computer program product for running software on an adapter. In response to a connection of a hardware interface for the adapter with a current host computer, a processor unit in the adapter determines whether a set of protocols for communicating with the current host computer to access resources is present on the adapter. In response to the set of protocols being absent on the adapter, the processor unit obtains the set of protocols from the current host computer. The processor unit identifies a set of available resources in the current host computer for use by the adapter using the set of protocols. The processor unit runs software stored on a set of storage devices in the adapter using the set of available resources identified for use by the adapter.

Growing community of inventors

Austin, TX, United States of America

Mysore Sathyanaranyana Srinivas