Panduit Corporation

Power-one Limited

Kulr Technology Corporation

Mysore Purushotham Divakar

Masud Bolouri-Saransar

Paul W Wachtel

Surendra Chitti Babu

David Keating

Antoin Russell

Satish I Patel

Paul B DuCharme

Ronald L Tellas

Nicholas G Martino

David E Urbasic

Ronald Alex Nordin

Thomas H Templeton, Jr

John Alan Maxwell

Robert Douglas Elliot

Michael Mo

Juergen Mueller

Surrendra Chitti Babu

Thomas Henry Templeton, Jr

A thermal electrical (TE) interface comprises a primary fiber thermal interface (FTI) having a first side configured to contact a heatsink, and a second side. The primary fiber thermal interface has a thickness ranging from 0.3 mm to 4 mm. A secondary fiber thermal interface (FTI) has a first side configured to contact the second side of the primary FTI, a second side configured to contact circuit components to dissipate heat from the circuit components through the first side of the primary FTI. The secondary fiber thermal interface has a thickness equal to or greater than the primary FTI.

Method and apparatus of operating a compressible thermal interface

An active patch panel uses small form factor plus (SFP+) connectivity with a plurality of channels extending between first and second faces of the panel. The channels connect ports on the opposing faces of the panel and are provided with additional electronic elements, such as an equalizer, a clock data recovery element, and a pre-emphasis element. A controller can be connected to the plurality of channels to provide instructions for simultaneous equalization and pre-emphasis of a plurality of cable assemblies in the same channel.

Active patch panel

A pair manager for use in securing a twin-axial cable to a printed circuit board is described. The pair manager comprises a generally block-shaped portion containing a pair of channels. The channels extend from the front face to the rear face of the block-shaped portion. An integral flange and a pair of integral fingers extend perpendicularly from the front face of the block-shaped portion. The flange extends generally from the center of the front face and the fingers extend from opposite edges of the front face. The fingers and flange function as a partial shield cavity around each pair of conductors. This design helps to maintain better impedance matching when connecting twin-axial cables to a printed circuit board.

Pluggable cable connector

The invention provides a subassembly to facilitate co-planar vertical surface mounting of subassembly boards. By 'vertically mounting' is meant that a subassembly circuit board with a major surface is mounted perpendicular to the major surface of a circuit motherboard. In accordance with the invention, a subassembly for co-planar vertical surface mounting comprises a subassembly board coupled between a pair of base headers. Advantageously one base header comprises a plurality of mounting lugs secured to a transverse element in a co-planar configuration. The other base header conveniently comprises a plurality of connector pins secured to an elongated header element in co-planar configuration. The two headers interlock with the board to provide connection and co-planar support. Edge metallization of the subassembly board can provide enhanced thermal or electrical connection to the underlying portions of one or more lugs.

Enhanced connection arrangement for co-planar vertical surface mounting of subassemblies on a mother board

The invention provides arrangements to facilitate surface mounting of subassembly boards on a motherboard with reliable, high conductivity interconnection. In accordance with the invention, the subassembly interconnection arrangement is composed of separate power and sense connector arms formed on one or more base headers. The arrangement interconnects and supports the subassembly board on the motherboard surface. Each power arm advantageously comprises a plurality of split-based mounting lugs secured to the arm in a coplanar configuration. Each sense connector arm preferably comprises a plurality of connector pins secured to the arm in a coplanar configuration. Embodiments are disclosed for vertical and horizontal surface mounting.

Arrangement for surface mounting of subassemblies on a mother board

A semiconductor chip package that includes a DC&#x2014;DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC&#x2014;DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array. The land grid array includes external pads that are separated into an interior region and a peripheral region. Each external pad located in the interior region of the land grid array is electrically and thermally coupled a via array.

DC-DC converter implemented in a land grid array package

A mounting structure for a semiconductor die that reduces die attach strain within the die attach material without sacrificing the electrical and thermal characteristics of the package. In one embodiment, the mounting structure comprises a die attach metallization layer, a solder mask, and a layer of die attach material. The solder mask forms a solder pattern over the top surface of the die attach metallization layer. The solder pattern covers a portion of the die attach metallization layer to create multiple exposed areas of the die attach metallization layer. Each exposed area is separated by the solder mask and is located under the semiconductor die when the semiconductor die is secured to the mounting structure. A layer of die attach material covers the solder pattern and fills in each one of the exposed areas to form a semiconductor die mounting surface. In another embodiment, the die attach metallization layer is divided into multiple, spaced-apart die attach pads that are electrically coupled together. A layer of die attach material covers a portion of each die attach pad and fills in the space between each die attach pad to form a semiconductor die mounting surface. A method of manufacturing the mounting structure is also disclosed.

System and method of reducing die attach stress and strain

A semiconductor chip package that includes a DC&#x2014;DC converter implemented with a land grid array (LGA) package for interconnection and surface mounting to a printed circuit board. The LGA package integrates all required active components of the DC&#x2014;DC power converter, including a synchronous buck PWM controller, driver circuits, and MOSFET devices. In particular, the LGA package comprises a substrate having a top surface and a bottom surface, with a DC&#x2014;DC converter provided on the substrate. The DC&#x2014;DC converter including at least one power silicon die disposed on the top surface of the substrate. A plurality of electrically and thermally conductive pads are provided on the bottom surface of the substrate in electrical communication with the DC&#x2014;DC converter through respective conductive vias. The plurality of pads include first pads having a first surface area and second pads having a second surface area, the second surface area being substantially larger than the first surface area. Heat generated by the DC&#x2014;DC converter is conducted out of the LGA package through the plurality of pads.

Growing community of inventors

San Jose, CA, United States of America

Mysore Purushotham Divakar