Altera Corporation

Myron Wai Wong

John C Costello

William Bradley Vest

Dirk Alan Reese

Irfan Rahim

Raminda U Madurawe

John E Turner

Thomas Henry White

James D Sansbury

Andy Louie Lee

Rakesh H Patel

Jeffrey T Watt

Chiakang Sung

Joseph Huang

Bonnie I Wang

Khai Nguyen

Xiaobao Wang

Wayne Yeung

Richard G Smolen

Weiying Ding

In Whan Kim

Krishna Rangasayee

Rafael Czernek Camarota

Mark Chan

Minchang Liang

Stephanie T Tran

Ping Xiao

Guu Lin

Mario E Guzman

Mian Z Smith

Robert R N Bielby

Bruce F Mielke

Mark W Fiester

Michael Hsiao-Ming Chu

W Bradley Vest

Gwen G Liang

William B &ldquo;Brad&rdquo; Vest

Min Maung

Im Whan Kim

Bruce E Mielke

Sriram Muthukumar

Neil Nghia Tran

Nima Gilanpour

Bruce E Mielk

Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.

Integrated circuit decoupling capacitors

Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.

Volatile memory elements with soft error upset immunity

Circuitry on an integrated circuit is provided that may be used to program fuses such as polysilicon fuses. Fuse programming may be performed using an elevated power supply voltage. Other circuitry on the integrated circuit may be powered using a standard power supply voltage that is less than the elevated power supply voltage. Fuse sensing may be performed using the standard power supply voltage. A control block may be used to produce a fuse programming control signal. Power-on-reset circuitry may monitor the elevated power supply voltage and may produce a corresponding elevated power supply voltage power-on-reset signal indicative of whether the elevated power supply voltage is valid. The power-on-reset circuitry may also produce a standard power supply power-on-reset signal indicative of whether the standard power supply voltage is valid. The power-on-reset signals may be used in controlling fuse programming and fuse sensing.

Integrated circuits with fuse programming and sensing circuitry

Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.

Configuration random access memory

A buffer circuit is disclosed. In one embodiment, the buffer circuit includes a preconditioning circuit and a driver circuit. The preconditioning circuit generates a pre-charge signal in response to receiving an input signal. After a predetermined duration, or when the pre-charge circuit reaches a threshold output signal level, the input signal is coupled to an input of the driver circuit. The output signal of the driver circuit is combined with the output signal of the preconditioning circuit to form a composite output signal of the buffer circuit. In one embodiment, the pre-charge signal is used to lower the effective VDS across the transistors of the driver circuit to reduce hot-carrier injection, and therefore reduce transistor performance degradation.

Precharge and discharge of I/O output driver

A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.

Look-up table overdrive circuits

Circuits, methods, and apparatus for limiting voltages received by devices in input/output cells to less than the device's breakdown voltage. An exemplary embodiment of the present invention provides an input/output cell having one or more clamp diodes and resistors configured to limit voltages seen by the gates of the devices in the input/output cell. In one embodiment, the clamp diodes are on-chip, while the resistors are off-chip. In a specific embodiment, the clamp diode is connected between an input pad for the input output cell and a supply voltage VCC, while a resistor is off-chip and in series with the input pad. In another specific embodiment, a series of clamp diodes are coupled between ground and an input pad, while a resistor is off-chip and in series with the input pad. In another embodiment, the clamp diode or diodes may be programmably or selectively disconnected. These clamp diodes may be disabled to protect against latch-up. Integrated circuits that are consistent with the present invention may include one or more of these and the other features described.

High voltage tolerance emulation using voltage clamp for oxide stress protection

Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.

Techniques for configuring programmable logic using on-chip nonvolatile memory

A split-gate memory cell includes a memory transistor and a select transistor. The memory transistor includes a drain, a source, a control gate and a floating gate. The select transistor includes a drain, a source and a select gate. The source of the select transistor is electrically connected to the drain of the memory transistor. The threshold state of the floating gate of the memory transistor determines the logic output of the memory cell. When the split-gate memory cell is erased or programmed a high voltage is only applied to the control gate and source of the memory transistor. As a result, no high voltage will be placed on any portion of the select transistor and the split-gate memory cell can achieve an increased cycling endurance.

Structure of a split-gate memory cell

Techniques are provided for reducing power consumption in memory cells. A static (SRAM) memory cell includes two cross coupled inverters. One or more transistors are coupled between the inverters and the power supply voltages. The transistors are turned OFF for a period of time during a memory state transition to block current flow between the high power supply voltage and the low power supply voltage to reduce power consumption.

Techniques for reducing power consumption in memory cells

The invention provides a high-speed buffer that may used at the input of an integrated circuit, such as an input buffer. This buffer may be configured for use as a standard buffer with a single switching threshold, such as a TTL-to-CMOS buffer, or used as a Schmitt trigger with hysteresis, which as at least two switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Input buffer with hysteresis option

Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.

Apparatus and method for margin testing single polysilicon EEPROM cells

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Fremont, CA, United States of America

Myron Wai Wong