Texas Instruments Corporation

Burr-brown Corporation

Burr-brown Research Corporation

Myron J Koen

Joel Martin Halbert

Ismail Hakki Oguzman

Harish Venkataraman

Thomas R Anderson

Arash Loloee

A system and method for providing a high voltage ultrasonic drive signal from an ultrasound transmitter are disclosed herein. An ultrasound transmitter includes a first driver and a bias network. The first driver includes a first plurality of drive transistors that when activated drive an ultrasound transmitter output to a first voltage. The first bias network is coupled to the first plurality of drive transistors, and, at least in part, controls distribution, across the drive transistors, of voltage at the ultrasound transmitter output. Control inputs of the first driver are decoupled from the ultrasound transmitter output.

High voltage ultrasound transmitter with symmetrical high and low side drivers comprising stacked transistors and fast discharge

A system and method for providing a high voltage ultrasonic drive signal from an ultrasound transmitter are disclosed herein. An ultrasound transmitter includes a first driver and a second driver. Each of the drivers includes an N-type device and a P-type device. The N-type device and the P-type device of each driver are serially coupled. Activation of the first driver drives an ultrasound transmitter output to a first voltage. Activation of the second driver drives the ultrasound transmitter output to a second voltage. The driver activations produce an ultrasonic drive signal at the ultrasound transmitter output.

High voltage ultrasound transmitter with symmetrical high and low side drivers comprising stacked transistors

A system and method for providing a continuous wave ('CW') ultrasonic drive signal and a B-mode ultrasonic drive signal from an ultrasonic transmitter are disclosed herein. An ultrasonic transmitter includes a first shunt transistor and a second shunt transistor. The first shunt transistor shunts positive transmitter output voltage to ground. The second shunt transistor shunts negative transmitter output voltage to ground. The shunt transistors include control inputs that, when modulated, cause the shunt transistors to produce a CW ultrasonic drive signal on a transmitter output. The ultrasonic transmitter also includes a first CW control transistor coupled to the first shunt transistor, and a second CW control transistor coupled to the second shunt transistor. The first and second CW control transistors respectively provide negative and positive CW drive voltage to the first and second shunt transistors.

Low power continuous wave ultrasound transmitter

A system and method for providing a high voltage ultrasonic drive signal from an ultrasound transmitter are disclosed herein. An ultrasound transmitter includes a first plurality of drive transistors. A bias network is coupled to at least one transistor of the first plurality of drive transistors. A first switch is coupled to the bias network. The first switch selectively connects a first voltage to the bias network. The first switch is closed when generating an ultrasonic drive signal. The first switch is open when the transmitter is not generating an ultrasonic drive signal.

Ultrasound transmitter

A circuit includes a first variable resistor having a resistance which is variable in response to a resistance control signal. A resistance control circuit includes a first current source circuit for supplying a first current through a reference resistor. A second current source circuit supplies a second current through the first variable resistor. In operational amplifier has a first input coupled to a first conductor connecting the first current source to the reference resistor, a second input coupled to a second conductor connecting the current source to the first variable resistor, and an output applying the first resistance control signal to a control terminal of the first variable resistor, to force the resistance of the first variable resistor to be equal to a resistance of the reference resistor. The resistance of a second variable resistor of an attenuator is controlled in response to the resistance control signal.

Process and temperature-independent voltage controlled attenuator and method

A method and circuit for eliminating input voltage offset in an amplifier circuit are provided. An exemplary offset correction circuit is configured with DC restoration to eliminate the DC input voltage offset by suitably providing a correction voltage to correct an input voltage offset during operation of the amplifier circuit, without realizing recovery time problems associated with AC coupling. An exemplary offset correction circuit is configured with DC restoration and comprises a timing circuit, a sample and hold circuit, and a feedback circuit to provide a correction voltage signal to correct input voltage offset. The timing circuit is configured to determine a 'dead time' and 'live time' for operation of the amplifier circuit. During the &#x201c;dead time&#x201d; period the sample and hold circuit will sample a differential signal across the DC coupling and provide a feedback signal through feedback circuit to correct input offset voltage. During the &#x201c;live time&#x201d; operation of the amplifier circuit, the sample and hold circuit operates to hold the level of correction voltage provided by the feedback circuit to suitably maintain a low input voltage offset.

Method and circuit for input offset correction in an amplifier circuit

A programmable gain low noise amplifier includes a tail current transistor (Q) having a source coupled to a first reference voltage (VDD) and a drain coupled to a tail current conductor () and, in a differential input embodiment, a plurality of pairs (Q, QQ, Q) of differentially coupled input transistors. Each pair includes a first input transistor having a gate coupled to a first input conductor (A) and a drain coupled to a first output conductor (A) and a second input transistor having a gate coupled to a second input conductor (B), a source coupled to a source of the first transistor, and a drain coupled to a second output conductor (B). The sources of the first and second input transistors of some or all of the pairs are selectively coupled to the tail current conductor () in it response to corresponding gain control signals (B).

Programmable low noise amplifier and method

A method and circuit for facilitating control of the AC coupling for addressing input offset in an amplifier circuit are provided. In accordance with an exemplary embodiment, a control circuit comprises a pair of resistive networks coupled together through a capacitive coupling, with the pair of resistive networks configured between two amplifier devices of the amplifier circuit. The capacitive coupling is configured to prevent offset in the differences between input voltages to the two amplifier devices, and can comprise various types and configurations of capacitor networks, devices and components. The pair of resistive networks is configured to generate an output current signal from the two amplifier devices while facilitating a substantially identical capacitive loading on the two amplifier devices.

Method and circuit for facilitating control of AC coupling in an amplifier circuit

The present invention discloses a circuit used to couple an input signal to an amplifier circuit. The circuit may contain a diode bridge coupled to an adjustable bias circuit. The current through the bias circuit can be adjusted such that the resistance of the diode bridge can be dynamically configured to change the sensitivity of the diode bridge. The bias circuit may be configured to produce a variable amount of current based on a voltage signal. In another aspect of the present invention, the output from the diode bridge is coupled to an amplifier via a clamp circuit designed to prevent the amplifier from overloading.

Programmable front end for a receiving channel

An amplifier with a electrically controllable gain and enhanced protection against an overload condition is disclosed. The amplifier contains a buffer amplifier configured to convert an input voltage signal to a current signal and an output amplifier that converts a current signal to an output voltage signal. The gain of the amplifier can be controlled by an internal resistor that can be electrically configured to different resistance levels. The amplifier also includes a clamping network used to clamp the output amplifier to prevent an overload condition. This network may take the form of a diode network. Such an amplifier may take the form of a differential amplifier.

Fast recovery time precision amplifier

A logarithmically controlled attenuator circuit includes a resistive attenuator having a single series resistive element connected between an input conductor and an output conductor, and a plurality of parallel resistive elements each having a first terminal connected to the output conductor. A plurality of switching elements controllably couple the parallel resistive elements, respectively, between the output conductor and a first reference voltage conductor. A control circuit produces successive gradually increasing and then leveling off analog control signals on the control terminals of successive switching elements, respectively. A programmable implementation includes a first group of parallel resistive elements (Q,. . . ) each having a first terminal connected to the output conductor (,), and a second group of parallel resistive elements (Q,. . . ) each having a first terminal connected to the output conductor (,).

Programmable low noise CMOS differentially voltage controlled logarithmic attenuator and method

A low noise differential amplifier includes a differential stage and first and second unbalanced differential feedback amplifiers. The differential stage includes first (13) and second (14) load devices coupled to first (11) and second (12) conductors, respectively, a resistor (RS), a first input transistor (Q1) having a first electrode coupled to the first conductor and a second electrode coupled by a third conductor (16) to a first terminal of the resistor (RS), and a second input transistor (Q2) having a first electrode coupled to the second conductor (12) and a second electrode coupled by a fourth conductor (17) to a second terminal of the resistor (RS). The first feedback amplifier (18) includes a third input transistor (Q5) coupled between the third conductor (16) and the first current source transistor (Q3). The first feedback amplifier (18) drives the control electrode of the first input transistor (Q1). The second feedback amplifier (19) receives an input signal (VIN-), and drives to control electrode of the second input transistor (Q2), the second feedback amplifier (19) producing a second signal (25) on the control electrode of the second input transistor (Q2). A first current source produces a first bias current through the first load device (13), the first input transistor (Q1), and the third input transistor (Q5). A second current source produces a second bias current flowing through the second load device (14), the second input transistor (Q2), and the second feedback amplifier.

Low noise differential input, differential output amplifier and method

A logarithmic attenuator circuit includes a resistive attenuator in which the series resistors are P-channel MOSFETs with gate electrodes connected to V.sub.DD and the parallel resistors are P-channel MOSFETs which also function as switches. A control circuit (8B) produces a plurality of successive control signals (V1,2 . . . 10) on the gate electrodes of the successive MOSFETs which functions as switches in response to a gain control signal (V.sub.GC)

CMOS differential voltage controlled logarithmic attenuator and method

A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The sampling waveform digitizer system comprises a sampling comparator for comparing a sampled input signal with a first signal. An integrator coupled to the comparator provides an output signal from the integrator and becomes the first signal. An analog to digital converter provides the digital representation of the analog waveform. A controllable delay is provided for selecting a period of time for sampling the input signal by the comparator. A control device is provided for controlling the time the comparator samples the input signal. These combination of system features allow the digitizer to receive high speed analog waveforms and convert them to an accurate digital representation of the previously described high speed analog waveform.

Sampling wave-form digitizer for dynamic testing of high speed data

A 12 bit, 10 megahertz subranging analog-to-digital converter produces a sampled analog input signal. The sampled analog signal is converted by an MSB flash encoder to a 7 bit MSB word that is converted to an analog signal by a 7 bit DAC having 14 bit accuracy. The result is subtracted from the sample analog signal to produce a residue signal by means of a high speed amplifier having first and second multiplexed differential input stages, the first input stage having differential inputs receiving the sampled analog input signal and the analog signal produced by the 7 bit DAC. The second differential input stage has one input connected to ground and the other input resistively coupled to the output of the high speed amplifier. The output of the high speed amplifier is resistively coupled to the second input of the first and second differential stages. The multiplexed input high speed amplifier produces an intermediate input level until the output of the DAC is stable. Amplifying of the residue signal then begins from a balanced amplifier condition, and avoids delays that might result from an initial overdriven amplifier condition.

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Tucson, AZ, United States of America

Myron J Koen