Samsung Electronics Co., Ltd.

Myoung-Won Yoon

Sang-Hyun Joo

Daeseok Byeon

Chiweon Yoon

Donghun Kwak

Won-Chul Lee

Jae-Hak Yun

Jae Woo Im

Oh-Suk Kwong

Eun-Kyoung Kim

Jong-Chul Lee

A nonvolatile memory device includes a memory block with an unused line connected to dummy cells and used lines connected to normal cells, and a controller which applies an erase voltage to the memory block, applies an unused line erase voltage to the unused line, and applies a word line erase voltage to the used lines during an erase operation. The dummy cells are not programmed during a program operation while the normal cells are programmed, the unused line erase voltage transits from a first voltage to a floating voltage at a first time point, and the controller reads the dummy cells and controls at least one of the magnitude of the first voltage and the first time point based on the result of reading the dummy cells.

Nonvolatile memory device and method of operating the same

A nonvolatile memory device includes processing circuitry configured to apply a sub-voltage to the first word lines, determine a desired first read voltage based on a threshold voltage distribution of a plurality of first memory cells connected to the first word lines, apply the sub-voltage to the second word lines, determine a desired second read voltage based on a threshold voltage distribution of a plurality of second memory cells connected to the second word lines, apply the desired first read voltage to the first word lines while simultaneously reading the first memory cells connected to the first word lines, and apply the desired second read voltage different from the desired first read voltage to the second word lines while simultaneously reading the second memory cells connected to the second word lines.

Nonvolatile memory device

A test system includes a non-volatile memory device that includes a plurality of memory blocks operating in a multi-plane mode, and a test machine that detects a bad block of the non-volatile memory device. The non-volatile memory device generates a ready/busy signal which is based on whether an erase loop for detection of the bad block progresses. When at least one normal block is detected from the plurality of memory blocks included in planes operating in the multi-plane mode, the non-volatile memory device generates the ready/busy signal having a first busy interval. When all the memory blocks included in the planes operating in the multi-plane mode are detected as bad blocks, the non-volatile memory device generates the ready/busy signal having a second busy interval shorter than the first busy interval.

Memory device and method for reducing bad block test time

A storage device includes a nonvolatile memory device including memory blocks and a controller configured to control the nonvolatile memory device. Each of the memory blocks includes a plurality of cell strings each including at least one selection transistor and a plurality of memory cells stacked on a substrate in a direction perpendicular to the substrate. The controller controls the nonvolatile memory device to perform a read operation on some of selection transistors of a selected one of the memory blocks and to perform a program operation on the selection transistors of the selected memory block according to a result of the read operation.

Storage device including nonvolatile memory device and controller

A method of storing data in a nonvolatile memory device comprises performing a program operation on target memory cells among multiple memory cells, performing a first verify operation to determine whether the target memory cells are in a program pass state or a program fail state, and as a consequence of determining that the target memory cells are in the program pass state, performing a second verify operation to determine whether the target memory cells exhibit a program error symptom.

Growing community of inventors

Suwon-si, South Korea

Myoung-Won Yoon