Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Samsung Mobile Display Co., Ltd.

Samsung Displayco., Ltd.

Myoung-Soo Kim

Min-Soo Choi

Myung-Soo Huh

Han-ki Kim

Kyu-Sung Lee

Seung-Young Choi

Seung-Wan Kim

Hwan-Woong Lee

Gwang-Teak Lee

Tae-Gon Im

Joon-Chul Goh

Kwang-chul Jung

Bong-Hyun You

Dae-Sik Lee

Taegon Im

Ho-Kyoon Kwon

Hee-Cheol Kang

Yun-Gun Lee

Sang-Ik Lee

Eun Chul Shin

Kyoung-Ho Lim

Hwanwoong Lee

Dal-Jung Kwon

Byung-kyou Min

Ki-Seok Cha

Kazuo Furuno

Jun-Ki Jeong

Sung-Dae Bae

Eui-Dong Hwang

Han-Ki Kim

A method of driving a light-source module includes adjusting a frequency of a boosting switching signal based on a dimming signal which controls luminance of a light-emitting diode ('LED') string of the light-source module, where the LED string comprises a plurality of LEDs connected to each other in series, and controlling a main transistor in response to the boosting switching signal to transfer a driving voltage to the LED string.

Method of driving light-source with improved contrast ratio and display apparatus for performing the method

A display apparatus includes a plurality of pixels arranged in columns and rows in a display area, a data line extending in a first direction and connected with pixels of a k-th column ('k' is a natural number) and a (k+1)-th column, a gate line extending in a second direction crossing the first direction and connected with ones of the pixels, a gate signal line extending in the first direction and connected with the gate line, and a gate driver in a first peripheral area adjacent to a first longer side of the display area and having a first width, and configured to apply a gate signal to the gate line.

Display apparatus

A method for manufacturing a display device includes: connecting a first printed circuit board and a second printed circuit board with a first connecting film, the first printed circuit board and the second printed circuit board configured to apply a driving signal to a display panel; attaching a fixing member to the first printed circuit board and the second printed circuit board, such that the first connecting film extends away from the display panel and the first printed circuit board is spaced apart from the display panel; attaching the second printed circuit board to the display panel with second connecting films; removing the fixing member; and attaching the first printed circuit board to the display panel.

Method for manufacturing display device

Method of driving light-source and display apparatus for performing the method

A backlight unit includes a power converter configured to generate a light source driving voltage in response to a voltage control signal, a plurality of light emitting diode strings, where each of the light emitting diode strings receives the light source driving voltage through a first terminal thereof, a plurality of transistors corresponding to the light emitting diode strings, where each of the transistors includes: a first electrode connected to a second terminal of a corresponding light emitting diode string thereof; a second electrode; and a control electrode, and a controller connected to the control electrode and the second electrode, where the controller outputs a plurality of current control signals to control electrodes of the transistors and generate the voltage control signal, where the controller generates an over-current detection signal when any one of the current control signals has a pulse width less than a predetermined reference width.

Backlight unit with over-current detection and display device having the same

A leakage current occurring on a boundary of a trench isolation region and an active region can be prevented in a Metal Oxide Semiconductor (MOS) Field Effect transistor, and a fabricating method thereof is provided. The transistor includes the trench isolation region disposed in a predetermined portion of a semiconductor substrate to define the active region. A source region and a drain region are spaced apart from each other within the active region with a channel region disposed between the source region and the drain region. A gate electrode crosses over the channel region between the source region and the drain region, and a gate insulating layer is disposed between the gate electrode and the channel region. An edge insulating layer thicker than the gate insulating layer is disposed on a lower surface of the gate electrode around the boundary of the trench isolation region and the active region.

Metal oxide semiconductor (MOS) field effect transistor having trench isolation region and method of fabricating the same

Methods of fabricating an organic light emitting device using plasma and/or thermal decomposition are provided. An insulating layer is formed by reacting first and second radicals. The first radical is formed by passing a first gas through a plasma generating region and a heating body, and the second radical is formed by passing a second gas through the heating body. The methods improve the characteristics of the resulting insulating layer and increase the use efficiency of the source gas by substantially decomposing the source gas. The insulating layer can be a passivation layer formed on an organic light emitting device. The methods use plasma apparatuses such as an inductively coupled plasma chemical vapor deposition (ICP-CVD) apparatuses or plasma enhanced chemical vapor deposition (PECVD) apparatuses.

Method of fabricating organic light emitting device

A balance board includes; a substrate, a first wire disposed on the substrate, a second wire disposed on the substrate and spaced apart from the first wire, a plurality of first balance coils connected to the first wire and which uniformly distribute a first power supply voltage, a plurality of second balance coils connected to the second wire and which uniformly distribute a second power supply voltage, and a conductive pattern disposed on the substrate and spaced apart from the first and second wires, wherein the first and second wires are disposed substantially in parallel with each other, the second wire being divided into a plurality of parts with respect to an area where the first wire and the second wire cross over one another and the plurality of parts of the second wire are connected by a plurality of jumper connectors overlapping the first wire.

Balance board and liquid crystal display having the same

A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.

Transistor, a transistor arrangement and method thereof

A catalyst-enhanced chemical vapor deposition (CECVD) apparatus and a deposition method, in which tension is applied to a catalyst wire in order to prevent the catalyst wire from sagging due to thermal deformation, and additional gas is used to prevent foreign material from being generated. The CECVD apparatus may be constructed with a process chamber, a showerhead to introduce process gas into process chamber, a tensile catalyst wire structure provided in the process chamber to decompose the gas introduced from the showerhead, and a substrate on which the gas decomposed by the catalyst wire structure is deposited, so that the tension is applied to a catalyst wire in order to prevent the catalyst wire from sagging due to thermal deformation, and additional gas is used to prevent foreign material from being generated, thereby eliminating occurrences of non-uniform temperatures of a substrate and non-uniform film growth, and concomitantly enhancing the durability of the catalyst wire.

Catalyst enhanced chemical vapor deposition apparatus and deposition method using the same

The present invention provides a catalytic enhanced chemical vapor deposition (CVD) apparatus capable of maximizing efficiency of gas use to 80% or more, and obtaining a uniform thin film by efficiently arranging filaments mounted on a shower head of the catalytic enhanced CVD apparatus, thereby uniformly decomposing a deposition source gas. The present invention also provides a method for fabricating an organic electroluminescent device with an inorganic film formed through the catalytic enhanced CVD apparatus.

Catalytic enhanced chemical vapor deposition apparatus having efficient filament arrangement structure

In one embodiment, a non-volatile memory device includes an isolation film defining an active region in a semiconductor substrate; a tunnel insulating film located on the active region; a control gate located on the isolation film; an inter-gate dielectric film parallel to the control gate and located between the control gate and the isolation film; an electrode overlapped by the control gate and the inter-gate dielectric film, wherein the electrode extends over the tunnel insulating film on the active region to form a floating gate; and a source region and a drain region formed in the active region on both sides of the floating gate.

Non-volatile memory device and fabrication method thereof

A method of forming an alignment key with a capping layer in a semiconductor device without an additional mask formation process, and a method of fabricating a semiconductor device using the same, may be provided. The method of forming an alignment key may include forming an isolation layer confining an active region in a chip region of a semiconductor substrate, and forming an alignment key having a step height difference with respect to the surface of the semiconductor substrate in a scribe lane. An at least one formation layer for forming an element may be formed on the substrate, and patterned, to form an element-forming pattern on the semiconductor substrate in the chip region, and a capping layer capping the alignment key on the semiconductor substrate in the scribe lane.

Method of forming an alignment key having a capping layer and method of fabricating a semiconductor device using the same

A semiconductor device with a one-time programmable (OTP) ROM disposed over a semiconductor substrate including a memory cell area and a peripheral circuit area includes a MOS transistor and an OTP ROM capacitor. The MOS transistor has a floating gate electrode and is disposed at the memory cell area. The OTP ROM capacitor has a lower electrode, an upper intermetal dielectric, and an upper electrode which are stacked in the order named. The OTP ROM capacitor is disposed on the MOS transistor, and the floating gate electrode and the lower electrode are connected by a floating gate plug to constitute an electrically insulated conductive structure. The upper intermetal dielectric is made of at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride and may be disposed on an entire surface of the semiconductor substrate. A capacitor formed together with the OTP ROM is disposed at the peripheral circuit region.

Growing community of inventors

Suwon-si, South Korea

Myoung-Soo Kim