Samsung Electronics Co., Ltd.

Myoung-soo Kim

Hyoun-Soo Kim

Seong-sik Min

Integrated circuit devices are provided. An integrated circuit device includes a substrate and a device isolation film on the substrate. An active region of the substrate is defined by the device isolation film on the substrate and has a first width in a horizontal direction. A gate electrode is on the active region and has a second width equal to or less than the first width of the active region in the horizontal direction. The integrated circuit device includes an insulating spacer over the device isolation film and the active region.

Integrated circuit devices

A semiconductor chip includes a substrate including a circuit area having a rectangular shape and a peripheral area surrounding the circuit area, a key area being overlapping a part of the circuit area and a part of the peripheral area, a plurality of drive circuit cells in the circuit area, and a conductive reference line on the peripheral area and extending in a first direction parallel to a first edge among four edges of the rectangular shape of the circuit area.

Semiconductor chips and semiconductor packages including the same

A display drive chip includes an electrostatic discharge (ESD) protection circuit unit configured to protect a circuit from ESD, an output including output pins for ouputting an output signal from a circuit disposed in an electric circuit region located in a central part of the display drive chip, a main voltage metal line electrically connecting the ESD protection circuit unit and the output to each other in the electric circuit region, an auxiliary voltage metal line that is connected to the ESD protection circuit unit and is disposed in a region of the chip outside the perimeter of the electric circuit region, and connection metal lines electrically connect the auxiliary voltage metal line and the output pins to each other.

Display drive chip

An analogue semiconductor device and a semiconductor IC device including the same include a substrate having a transistor, a MIM capacitor electrically separated from the transistor on the substrate and having a lower electrode, a dielectric layer and an upper electrode, interlayer insulation covering the transistor and the MIM capacitor and a BEOL resistor connected to the upper electrode and equipotential with the lower electrode. The BEOL resistor has a relatively large and easy-variable resistance with minimized parasitic capacitance between the resistor and the lower electrode of the MIM capacitor.

Semiconductor device having a resistor and semiconductor integrated circuit devices using the same

A semiconductor chip having an improved structure without an investment in photolithography equipment, a method of manufacturing the semiconductor chip, and a semiconductor package and a display apparatus which include the semiconductor chip are described. The semiconductor chip includes a circuit region disposed in a central part of a rectangle that is elongated in a first direction. The circuit region includes a plurality of driving circuit cells disposed at predetermined intervals in the first direction. A plurality of electrode pads is disposed around the circuit region, and a process pattern is disposed at at least one of the four sides of the rectangle.

Semiconductor chip, method of manufacturing the semiconductor chip, and semiconductor package and display apparatus including the semiconductor chip

A semiconductor device, which may be included in a display driver integrated circuit (IC) and a display device, includes a first interconnection and a second interconnection extending on a substrate and separate from each other, a third interconnection extending at a first level that is higher than a level at which the first interconnection and the second interconnection are disposed, and a fourth interconnection extending at a second level that is higher than the first level. A first contact plug is configured to connect the first interconnection and the third interconnection to each other. A stacked contact plug includes a second contact plug and a third contact plug, wherein the second contact plug is connected to the second interconnection, and the third contact plug is connected to the second contact plug and the fourth interconnection.

Semiconductor device, display driver integrated circuit including the device, and display device including the device

Methods of simultaneously forming MOS transistors and a capacitor on a substrate having gate insulation layers of varying thicknesses. A method includes forming field regions in a substrate to define a first transistor region, a capacitor region, and a second transistor region, forming a first gate stack in the first transistor region and a lower electrode in the capacitor region, and forming an upper electrode on the lower electrode with a dielectric layer interposed therebetween and a second gate stack in the second transistor region.

Method of forming MOS transistor

The present invention includes a semiconductor device having a shallow trench isolation and a method of fabricating the same. The semiconductor device includes a gate electrode being arranged to cross over the active region. An oxide pattern is interposed between the active region and the edge of the gate electrode. The oxide pattern defines a channel region under the gate electrode. A lightly doped diffusion layer is formed in the active region downward and outward from the oxide pattern, and a heavy doped diffusion layer is formed in a predetermined region of the active region and surrounded by the lightly doped diffusion layer. In the method of fabricating the semiconductor substrate, a trench isolation layer is formed at a predetermined region of a semiconductor substrate to define an active region. A pair of preliminary lightly doped diffusion layers are formed in a line to cross over the active region. Then, oxide patterns are formed to cover at least the preliminary lightly doped diffusion layers. The oxide pattern defines a channel region. A gate oxide layer is formed on the channel region and a gate electrode is formed to cover the channel region and to cross over the active region. The edge of the gate electrode is over the oxide pattern. A heavy doped diffusion layer is formed in the active region of both regions of a gate electrode and shallower than the lightly doped diffusion layer.

Semiconductor device having a shallow trench isolation and method of fabricating the same

A semiconductor device having an align key, which is simultaneously formed by implanting ions before defining an active region, for a precise alignment with a preformed well on a semiconductor substrate when forming a photoresist pattern for defining the active region, and a method for manufacturing the same are provided The semiconductor device includes the align key formed of a first recess having a first depth from a surface of a semiconductor substrate in a scribe line region of the semiconductor substrate, and a second step portion formed by a second recess having a second depth, which is less than or equal to the first depth, from the surface of the semiconductor substrate in a well region of the semiconductor substrate.

Semiconductor device having align key for defining active region and method for manufacturing the same

A method of fabricating a semiconductor device applies a LOCOS profile characteristic to an edge portion of an STI in a HV region to thereby lower compressive stress that is concentrated on the side of the STI. A field oxide film is formed so that only edge portions of HV region (active region II) may be in contact with a comparatively stiff STI, and then, a thick gate oxide film is formed on the HV region by utilizing a nitride film as a mask. After the nitride film as a mask is removed, a thin gate oxide film is formed on a LV region (an active region I in which a thin gate oxide film is formed). As a result, a thinning phenomenon of a gate oxide film at an edge portion of STI is prevented that otherwise would occur when the gate oxide film for HV grows in a normal STI structure by utilizing a nitride film as a mask. The present invention also prevents compromise of the operational characteristics of a resulting transistor, which otherwise would be caused by the concentration of electric field and by the hump phenomenon.

Semiconductor device fabricating method

Disclosed is a method of selectively forming a silicide film of merged DRAM logic by which active regions of a logic side are entirely changed into a silicidation state without adding a separate photoresist patterning process even though there exist any regions in which the space between gates is somewhat narrower than in a DRAM cell forming region, and an etch stopper film of SiON material that is needed in the formation of deep contacts can be applied to a MDL process having dual gate in mass production.

Growing community of inventors

Hwaseong-si, South Korea

Myoung-soo Kim