Samsung Electronics Co., Ltd.

Myoung-Bum Lee

Byung-Hee Kim

Hyeon-Deok Lee

Jong-Myeong Lee

Jin-Gyun Kim

Eun-ae Chung

Gab-Jin Nam

Gil-Heyun Choi

Kyung-Tae Jang

Ji-Youn Seo

Gil-heyun Choi

Byung-Lyul Park

Yong-Chae Jung

Young-Pil Kim

Woong-hee Sohn

Chang-Won Lee

In-seon Park

Jong-Wan Choi

Chang-Gyu Kim

U-In Chung

Bean-Jun Jin

Chang-Gee Hong

Sang-Hoon Lee

Ki-Hyun Hwang

Han-Mei Choi

Hee-Sook Park

Jong-myeong Lee

Bo-Young Lee

Se-hoon Oh

Young-Geun Park

Ki-yeon Park

Kwang-jin Moon

Hauk Han

Seung-Mok Shin

Sug-Hun Hong

Yong-Il Kwon

Jun-Noh Lee

Tae-Jong Han

Ju-Wan Kim

Si-Hyung Lee

Sang-Ryol Yang

Kyong-Won An

Il-Woo Kim

Jeong-gil Lee

Ju-young Yun

Jin-gi Hong

Sung-Hae Lee

Dong-chul Yoo

Min-kyung Ryu

Ji-Woon Im

Koong-Hyun Nam

Bo-young Lee

Hyun-Yong Go

Dae-Hun Choi

Byong-ju Kim

Seon-ho Jo

Beom-jun Jim

In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Vertical memory devices and methods of manufacturing the same

A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.

Memory device and method of manufacturing the same

A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods

A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.

Vertical semiconductor devices

A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

Non-volatile memory devices including low-K dielectric gaps in substrates

A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.

Nonvolatile memory device and method of fabricating the same

Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

Methods of manufacturing semiconductor devices including metal oxide layers

Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.

Semiconductor having buried word line cell structure and method of fabricating the same

A non-volatile memory device includes a tunnel insulating layer pattern on a channel region of a substrate, a charge trapping layer pattern on the tunnel insulating layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode including a conductive layer pattern on the blocking layer pattern and a barrier layer pattern on the conductive layer pattern. The conductive layer pattern includes a metal.

Non-volatile memory device and method of manufacturing the same

A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS transistor includes a second gate conductive layer. The first gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.0 eV to about 4.3 eV. The third gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.7 eV to about 5.0 eV.

Complementary metal-oxide-semiconductor transistor including multiple gate conductive layers and method of manufacturing the same

A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes a first gate conductive layer pattern and a second gate conductive layer pattern. The first gate conductive layer pattern has a nitrogen concentration gradient gradually increasing from a lower portion of the first gate conductive layer pattern to an upper portion of the first gate conductive layer pattern. The second gate conductive layer pattern includes a material having a resistance substantially lower than a resistance of the first gate conductive layer pattern.

Semiconductor device and method of manufacturing the same

A heating chamber which can be used during a reflow process to form a metal wiring having a multi-layered writing structure and a method of heating a wafer using the same, are provided. The heating chamber is movable upward and downward between the upper process position and the lower loading position, and includes a pedestal having a supporting surface for supporting a wafer, a cover installed above the pedestal to form a processing area together with the supporting surface when the pedestal is placed in its raised process position and a heating unit for heating the waver. In the method of heating the wafer, the temperature in the processing area is maintained suitable for heating the wafer before the wafer is loaded onto the supporting surface, the wafer is loaded onto the supporting surface and the loaded wafer is heating in the processing area.

Heating chamber and method of heating a wafer

Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

Semiconductor devices having contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus

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Seoul, South Korea

Myoung-Bum Lee