Samsung Electronics Co., Ltd.

Myong-Jae Kim

Ji-Ho Cho

Won-Ju Lee

Jong-Mun Choi

Dong-Woo Sohn

Seung-Keun Lee

Tae-Sung Jung

Jin-Sung Park

Hwi-Taek Chung

Doo-Sub Lee

Dong-Ho Park

Jei-Hwan You

Mi-Young Woo

Yeon-Bae Chung

Seong-Don Hwang

Provides is a multi-chip package including a plurality of semiconductor memory devices. Each of semiconductor memory devices includes a register and a control circuit. The register is configured to store start sequence information representing start of execution of a refresh operation in the multi-chip package. The control circuit is configured to control start of the execution of the refresh operation in response to the start sequence information stored in the register. Since the start of the execution of the refresh operation is performed in sequence of respective semiconductor memory devices according to the start sequence information stored in the register, consumption of peak current may be reduced in a power saving mode.

Semiconductor memory device for use in multi-chip package

A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are included. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.

Low power multi-chip semiconductor memory device and chip enable method thereof

A flash memory device and related method of operation are provided. The device generally comprises a word line voltage generator circuit configured to generate a word line voltage based on incremental step pulse programming; and a word line voltage controller circuit that controls the word line voltage generator circuit so that either the unit program time or the increment size of the word line voltage is varied according to the number of program data bits among the set of input data bits that the device will store in memory cells.

Flash memory device capable of reduced programming time

A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.

The invention disclosed herein is a non-volatile memory device. The non-volatile memory device comprises: a first transistor connected between a first voltage and a control node, and controlled by a second voltage; a second transistor connected between the first voltage and the control node, and controlled by a third voltage, and a word line driver for driving a word line in responsive to a voltage of the control node. The second voltage is set to a ground voltage during an erase operation. The third voltage is set to a power voltage during the erase operation.

Row decoder circuit for use in non-volatile memory device

A nonvolatile integrated circuit memory device includes a memory cell array having a plurality of memory cells. A high voltage generating unit generates first, second, and third program voltages used in programming the memory cell array. A program control unit controls times of applying the second and third program voltages to the memory cell array responsive to the first program voltage. Programming methods for the nonvolatile integrated circuit memory devices are also provided.

Nonvolatile integrated circuit memory devices having staged application of program voltages and methods for programming the same

A flash memory device includes a write driver for driving a data line according to data to be written in a flash memory cell during a program period, a sense amplifier circuit for sensing and amplifying the data stored in the flash memory cell during a program verify period, and an insulation circuit for electrically insulating the sense amplifier circuit from the data line during an operation period of the write driver.

Flash memory device

A flash memory device is disclosed that includes a control circuit for generating a count-up pulse signal notifying a generation of an address required for a burst read operation. An address generator circuit generates an address in response to the count-up pulse signal, and a discharge circuit discharges global bit lines in response to the count-up pulse signal. According to this control scheme, the global bit lines may be discharged before the local and global bit lines are selected.

Flash memory device capable of reducing read time

The disclosure is a nonvolatile semiconductor memory including bitlines connected to memory cells and high-voltage specified NMOS transistors connecting the bitlines to sense amplifiers. Column selection signals applied to the NMOS transistors are established at a voltage higher than a power supply voltage during a read operation. In the case of power supply voltage drain, the invention prevents degradation of the drivability of the NMOS transistors.

Low-power nonvolatile semiconductor memory device

A method for reducing programming time of a nonvolatile semiconductor device is provided. In the method, after a plurality of memory cells are programmed by n-bit units, the memory cells are checked to determine whether the programming is completed. If any memory cell fails the programming operation, the reprogramming of the memory cells are performed. For the reprogramming, the n is multiplied by 2, wherein n is an integer not less than 2. Otherwise, if all the memory cells complete the programming or the number of the program operation gets to the maximum value, the memory cells finish the program operation. Accordingly, the method can reduce time for programming of the memory cells.

Nonvolatile semiconductor memory device and programming method therefor

A boosting unit comprises a plurality of boosting circuits. Each boosting circuit includes an input driving circuit, a switching circuit, a capacitor circuit, and a precharge circuit. The input driving circuit drives a corresponding external boosting signal. The switching circuit transfers either a power supply voltage, a ground voltage, or a boosting signal from one of the other boosting circuits to the capacitor circuit under the control of the corresponding external boosting signal. The capacitor circuit boosts up a boosting node, which has been precharged to a power supply voltage level by the precharge circuit, to predetermined voltage level higher than an input voltage level. The boosting circuits are connected together in series and simultaneously carry out a boosting operation. The boosting unit therefore provides a desired boosted voltage level at high speed.

Boosting circuit of semiconductor memory device

Disclosed is a semiconductor memory device having the least pin counts per chip to test the maximum number of chips in a single wafer at a time. The semiconductor memory device includes an address counter generating a plurality of address signals in response to a signal provided from the outside, an address selection circuit controlling a path of the address signals, a plurality of switches divided in a predetermined number of switch groups and connected between a memory array and data input/output pins, and a switch control circuit generating switch control signals to control a switching operation of the switch groups. A portion of the data input/output pins is employed in correspondence with the number of the switch groups.

Testable nonvolatile semiconductor device

In a system having a synchronous flash memory device which shares a system bus with a synchronous random access memory device, the synchronous random access memory device is set to refresh mode before a program or erase operation is performed in the synchronous flash memory device, thereby preventing the program and erase operations of the synchronous flash memory device from affecting the operation of, or data stored in, the synchronous random access memory device. After the program or erase operation is completed, the synchronous random access memory device is placed back in normal mode.

Growing community of inventors

Suwon-si, South Korea

Myong-Jae Kim