Samsung Electronics Co., Ltd.

Myeongo Kim

Kwangil Park

Jongwan Kim

Dongmin Kim

Hohyun Shin

Youngsoo Sohn

Hyunsung Shin

Hyungi Kim

A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.

Semiconductor memory device and memory system including the same

Growing community of inventors

Hwaseong-si, South Korea

Myeongo Kim